SK hynix plans to keep shrinking its existing 6F² DRAM structure with EUV (extreme ultraviolet) lithography while also developing 4F² and 3D DRAM, according to Yonhap News's report on the company's October 28, 2026 earnings call. SK hynix has already published research results on a 4F² structure, but this explanation does not mean mass production is starting. The names 6F² and 4F² describe the planar area of a DRAM cell relative to the minimum feature size F. Keeping a 6F² structure therefore does not mean scaling has stopped. To compare each company's strategy accurately, it helps to separate three different levers: shrinking the feature size, changing the cell structure, and rearranging peripheral circuitry.
Extending 6F² while developing next-generation technology
According to Yonhap News, SK hynix said it will make the most of the existing 6F² structure, drawing on the maturity and stability of its manufacturing process. The company said EUV lithography leaves room to shrink the 6F² structure further, while it also develops 4F² and 3D DRAM. In other words, it plans to keep improving a proven cell structure while preparing for an eventual move to new ones.
When a DRAM cell's planar area is written as nF², there are two main ways to make it smaller. One is to shrink the feature size F while keeping the coefficient n. The other is to change the cell structure so the coefficient itself falls. A 6F² cell shrinks as F gets smaller, while moving to 4F² changes the coefficient from 6 to 4. This means that when comparing 6F² and 4F² cells from different generations, the name alone cannot tell you which cell is smaller.
In a presentation timed with the June 2025 VLSI Symposium, SK hynix described 4F² as a cell area of 2F × 2F and outlined a direction of introducing vertical gates and 3D DRAM at 10nm-class and below. The latest explanation does not mean those new structures are being abandoned. Yonhap News also reports the company's view that technical feasibility of a new cell structure must be considered separately from its actual adoption and commercialization in products. Even if operation is confirmed at the research stage, that does not immediately make it a mass-production technology.
Shrinking F versus changing the cell structure
To understand the difference between 6F² and 4F², compare two cases: changing only the coefficient at the same feature size, and keeping the 6F² structure while shrinking F. Because cell planar area is the product of the coefficient and the square of F, depending on how much F shrinks, a 6F² cell can end up smaller than a 4F² cell built with a larger feature size. Writing F₆ for the 6F² feature size and F₄ for the 4F² feature size, the two areas are equal when 6F₆² = 4F₄². Solving gives F₆/F₄ = √(4/6) ≈ 0.8165.
Concretely, set the baseline 6F₀² cell area to 100, then compare a 4F² structure at the same feature size F₀ with a 6F² structure whose F has been reduced by 20%. The 20% reduction is an assumption set by the editorial team to illustrate the point; it is not an achievement or development target announced by SK hynix. Using the 4F² definition from the company's 2025 presentation and calculating only cell planar area gives the following.
| Comparison condition | Cell planar area formula | Area index (baseline = 100) |
|---|---|---|
| Baseline 6F² | 6F₀² | 100 |
| 4F² at the same F | 4F₀² | 66.7 |
| 6F² retained, F reduced by 20% | 6(0.8F₀)² | 64 |
The area index is each cell area divided by the baseline 6F₀², multiplied by 100. At the same feature size, a 4F² cell is about 33.3% smaller than a 6F² cell. However, because the effect of shrinking F scales with its square, a 6F² structure with F reduced by 20% has an area index of 64, slightly below the 66.7 of a 4F² structure at the original feature size. By this calculation, reducing F in the 6F² structure by about 18.4% from the baseline yields the same cell area as a 4F² structure at the baseline dimension.
This, however, is a mathematical comparison of different structures, not a measurement of actual products. It does not account for how capacitors and wiring are implemented or for the area occupied by peripheral circuits, and it excludes manufacturing complexity, yield, and cost. It therefore does not mean that moving to a 4F² structure shrinks the entire DRAM chip by about 33%, or that manufacturing costs fall by the same proportion. To compare the real integration density of products, you need to check each generation's feature size F as well as the overall chip configuration, including circuits outside the cell.
Wafer bonding puts peripheral circuits beneath the cells
In its 2025 presentation, SK hynix also introduced wafer bonding technology that places peripheral circuits beneath the cell region. This is different from technology that reduces the planar area of the cell itself. It combines the cell region and the peripheral circuits, traditionally placed on the same plane, in a vertical stack. Figures such as 6F² and 4F², which describe cell area, cannot tell you how peripheral circuits are arranged.
A research explainer the company published on July 27, 2026 presents results from Joodong Park on 4F² vertical-gate DRAM at VLSI 2026. The research team bonded wafers together and provided electrical connections between them, building a structure with peripheral circuits placed beneath the memory cells. In addition to evaluating electrical characteristics, they reportedly demonstrated actual read and write operations. This is an operational demonstration at the research stage, however, and yield and manufacturing cost for a mass-produced product have not been confirmed.
Countermeasures for the electrical challenges of denser cells are also being explored. According to the company's explainer, using a shared back gate makes it possible to control transistor threshold and interference from adjacent word lines without increasing cell area, but it also brings trade-offs such as degraded on-current and subthreshold characteristics. Bit lines also have a shield structure to suppress noise caused by coupling between wires. Making cells smaller is not enough; design that maintains read/write stability and electrical performance is essential.
Note also that "vertical" and "3D" in DRAM technology mean different things depending on what is being made three-dimensional. A vertical gate refers to the transistor structure itself, while placing peripheral circuits under the cell refers to a way of combining circuits vertically. 3D DRAM, by contrast, integrates the memory cells themselves in three dimensions, and it is also distinct from HBM (high-bandwidth memory), which stacks finished DRAM dies. These technologies are related, but they should not be treated as the same thing.
SK hynix and Micron take different views on 4F²
When comparing DRAM makers' technology strategies, the choice of cell structure and the adoption of wafer bonding also need to be considered separately.
On page 16 of its October 21, 2026 technical briefing materials, Micron said that although it has researched 4F² structures for more than 20 years, it will not pursue them going forward because of manufacturing complexity and rising costs. The 6F² extension and 3D DRAM development plans Micron presented, however, include wafer bonding and High-NA EUV. Deciding not to adopt a 4F² structure therefore does not mean forgoing wafer bonding itself. The two companies' approaches can be summarized as follows.
| Item | SK hynix | Micron |
|---|---|---|
| 6F² / 4F² policy | Yonhap News reported that at the October 28 call it described extending 6F² while developing 4F² and 3D DRAM in parallel | Its October 21 official materials say it will not pursue 4F² and will continue extending 6F² and developing 3D DRAM |
| Role of wafer bonding | In 4F² vertical-gate DRAM research, peripheral circuits beneath the cells are built using wafer bonding and inter-wafer connections | Wafer bonding is listed in the future 6F² roadmap |
| Stage of technical demonstration | July official research explainer describes demonstrated electrical characteristics and read/write operation | Shown in a diagram of future development directions, with a note that it does not indicate a specific introduction date |
The two companies have made different decisions on adopting 4F², but both include wafer bonding among the options for future development. Still, the structure SK hynix demonstrated at the research stage and the technology Micron presented as a future development direction cannot be compared as having reached the same stage. Micron's materials alone do not reveal details of its bonding structure, so it cannot be concluded that the two companies will use the same method or achieve equivalent performance or manufacturing cost. What they do share is treating the choice of cell structure and the arrangement of peripheral circuits as separate technical challenges.
On page 17 of the same materials, Micron also laid out a plan to start up its next-generation DRAM manufacturing technology "1δ" in the second half of 2027, improving bit density by the mid-20% range over the current 1γ generation. This is a company development target comparing bit density between generations, and it differs in both metric and baseline from the "20% reduction in F" assumed in the calculation above. And the stated timing for 1δ does not mean the wafer bonding and 3D DRAM described on page 16 will arrive at the same time. The company has not given specific introduction dates for those future technologies.
According to Yonhap News, SK hynix said that before adopting a new cell structure in products, it must verify not only performance and reliability but also yield and manufacturing cost, and go through product design and customer evaluation. The latest explanation did not reveal when 4F² or 3D DRAM might be commercialized, nor how many more generations the existing 6F² structure can serve. The focus ahead is not only which cell structure each company chooses, but how well it can combine actual feature sizes and circuit layouts to stably mass-produce high-performance, low-cost products. Ultimately, economics per good bit, which accounts for yield and manufacturing cost as well as chip integration density, is likely to be an important yardstick for evaluating each company's technology strategy.