Etched, a company developing AI inference chips, raised a $300 million Series C on July 23, 2026. The round was led by Sequoia Capital, with SK hynix also joining as an investor. The stated use of funds foregrounded in this announcement is manufacturing and continued deployment of the company's first-generation product. Etched has already begun manufacturing several hundred million dollars' worth of inference clusters, and has built a new 10MW lab for this purpose.
SK hynix's participation stands out because Etched is designing a new memory hierarchy built around HBM (High Bandwidth Memory). Etched's concept involves restructuring HBM and SRAM into cluster-scale shared memory to shorten data movement during inference. For an HBM manufacturer, this represents a touchpoint with the memory hierarchy extending beyond the accelerator itself. However, the two companies have not announced any HBM supply agreement or joint development.
The $300M Heads Toward Initial Production
The pre-money valuation for this round was $10 billion, and with the $300 million added, the post-money valuation reaches $10.3 billion. As of June 30, Etched had announced that it had secured $800 million across four previous funding rounds. Adding this round brings the cumulative total raised to $1.1 billion. Since the post-money valuation as of December 2025 was $5 billion, the valuation has more than doubled in roughly seven months.
What Etched foregrounds as the basis for this fundraising is over $1 billion in signed customer contracts. However, this is not recognized revenue. The company has not disclosed customer names, contract terms, delivery or cancellation conditions, or the timing of revenue recognition. To support a $10.3 billion valuation, one would need to verify the process by which contracted amounts actually convert into rack shipments and recurring revenue.
The product has moved past the design-blueprint stage. According to Etched, A0 silicon manufactured on TSMC's N4P process is operational, and the company is validating its first rack-scale product with customers. Lead investor Sequoia Capital states that the first batch of chips was stood up as a cluster within 40 days, and that early customers have begun gaining access. That said, A0 being operational, customer validation, and early access are not the same stage as mass-volume shipment to a broad customer base.
LVI Targets Prefill, CSM Targets Decode
Inference for large language models has two phases with different load characteristics: prefill, which processes the entire input prompt at once, and decode, which generates output one token at a time. Prefill runs dense matrix operations, making it easy to utilize compute performance. Decode, on the other hand, repeatedly reads the KV cache—the intermediate state derived from prior tokens—and is strongly affected by memory bandwidth and transfer latency.
| Inference Phase | Primary Constraint | Etched's Design |
|---|---|---|
| Prefill | Compute density, power, heat | Low Voltage Inference (LVI) |
| Decode | Memory capacity, bandwidth, inter-chip latency | Cluster Scale Memory (CSM) |
LVI reportedly lowers the voltage of compute blocks to less than half that of typical AI chips, suppressing clock throttling caused by power and heat. Etched claims that for trillion-parameter-class sparse Mixture of Experts (MoE) models, this allows the chip to sustain over 80% of Peak FLOPs without triggering thermal throttling. Achieving this requires unified design spanning from the compute circuitry through power delivery and cooling, along with coordinated packaging and scheduling.
CSM is a low-latency shared memory pool accessible from multiple chips within the same high-speed interconnect domain. Etched states that its proprietary interconnect combined with a hybrid HBM/SRAM configuration achieves both HBM's capacity and SRAM's low latency. The public explanation does not state that the KV cache itself disappears. At minimum, there is not yet grounds to conclude that CSM is a technology that eliminates the need for a KV cache.
Rebuilding Hardware, Rather Than Two-Stage Separation
The idea of separating prefill and decode is not unique to Etched. DistServe, presented at OSDI 2024, demonstrated that processing both phases on the same GPU pool causes latency and resource allocation to interfere with each other. NVIDIA's inference framework Dynamo also assigns prefill and decode to separate GPU workers, transferring the generated KV cache between VRAM via NVLink or InfiniBand.
Existing GPU clusters separate these two workloads through software placement and high-speed networking. Etched instead assumes distinct workloads from the outset, assigning LVI—which raises compute density through low voltage—to the prefill side, and CSM, extended across the entire cluster, to the decode side. The competitive question is not whether separation exists, but how far dedicated chips and shared memory can push down the cost of passing state between the two phases.
There remain many gaps to verify here. Etched has not disclosed the HBM generation and capacity, or the SRAM capacity, used in CSM. The interconnect's bandwidth and latency are also unknown. Beyond how memory consistency is maintained and how fault domains are isolated, power consumption per rack is also unclear. Latency characteristics when the shared range is extended to long contexts or large-scale MoE models have not been disclosed, and whether they can be kept consistent remains unconfirmed.
For SK hynix, Not the Next Step Beyond HBM, But How HBM Is Used
On July 3, SK hynix outlined its "full-stack AI memory creator" strategy, designing AI memory as a tiered system where HBM, DRAM, and eSSD work in concert. The explanation is that while training benefits from bandwidth near the accelerator, inference is more strongly affected by response speed, power efficiency, data access, and context retention. The investment in Etched aligns with the direction of this strategy.
The company also continues to advance HBM performance. HBM4, for which mass-production readiness was announced in September 2025, reportedly doubles I/O to 2,048 pins compared to the previous generation, doubling bandwidth and improving power efficiency by over 40%. Operating speed also exceeds 10Gbps. CSM is not a concept that retires such HBM; rather, it is a proposal to combine it with SRAM and inter-chip connections to remake capacity and latency as seen from the cluster level.
However, how much SK hynix invested this time has not been disclosed. Whether Etched will adopt SK hynix-manufactured HBM, or whether the two companies will jointly design memory or packaging, also remains unknown. At present, the only confirmed commercial relationship is that SK hynix participated in the Series C. Capital participation cannot be read as a supply agreement.
Beyond the 10MW Lab, Public Benchmarks
Etched has begun manufacturing several hundred million dollars' worth of inference clusters and has established a 10MW lab 15 minutes from its headquarters. The company has a factory in Taiwan, while its San Jose headquarters houses a data center, test house, and NPI prototyping lab. The plan calls for the first racks to ship in summer 2026, with a path toward gigawatt scale in 2027.
While production capacity has grown, materials for externally comparing performance remain insufficient. Etched states that throughput, latency, and power efficiency reached top-tier levels in early customer testing. However, the company has not disclosed the target models, numerical precision, or batch sizes used. Rack configuration, power consumption, and points of comparison also remain unknown. Sequoia's assessment that the product is "ahead on industry-standard throughput and interactivity curves" is likewise not accompanied by a reproducible graph.
With the $300 million raised, Etched has secured the funding to move from a working A0 chip to initial production. If the summer 2026 shipment materializes, and if figures compared against GPU clusters under the same model, precision, and power conditions are made public, it will become possible to judge whether the $10.3 billion valuation anticipated a genuine shift in inference infrastructure—or simply priced in expectations for early-stage mass production.