TSMC's cutting-edge "A14" process (roughly 1.4nm-class) has been the subject of conflicting reports regarding its trial production and mass-production timelines. Piecing together information from Taiwan's semiconductor supply chain sources and major media reports, it appears TSMC is on track to begin trial production in 2027, with full-scale high-volume manufacturing (HVM) targeted for late 2028. This timeline differs from reports by some overseas tech outlets claiming that "pilot production has already begun."
What stands out is TSMC's decision to skip ASML's next-generation High-NA EUV (numerical aperture 0.55) for A14, opting instead to rely on existing Low-NA EUV (NA 0.33) combined with multi-patterning. This approach avoids the high cost of High-NA EUV equipment and the exposure-field limitations that come with its anamorphic optics, while aiming to balance yield and manufacturing cost by extending proven technology.
TSMC also plans to bring a derivative process called "A13" into mass production in 2029. A13 will build on A14's design assets while shrinking linear dimensions to 97%. Unlike Intel, which is racing to adopt High-NA EUV for its leading-edge process, TSMC is taking a strategy of incremental miniaturization that leans on mature manufacturing technology.
A14 Trial Production in 2027, Mass Production in Late 2028
Some overseas tech media have reported that "TSMC has already begun pilot production of 1.4nm chips," but this differs somewhat from reporting out of Taiwan.
According to Taiwan's Economic Daily News, citing industry sources, trial production of the A14 process is scheduled to begin in 2027. At this point, a product-oriented trial line is not yet operational; instead, R&D lines are reportedly conducting early-stage verification work such as materials evaluation and transistor structure testing.
In 2027, TSMC plans to first bring a trial line online at Fab 20 in the Baoshan area of the Hsinchu Science Park. Fab 20 also serves as a key R&D and manufacturing site for the 2nm (N2) process, and it is where initial A14 trial work will take place.
Equipment for full-scale mass production will subsequently be rolled out to Fab 25, which is under construction in the Central Taiwan Science Park in Taichung.
Fab 25 is planned to house four buildings—P1 through P4—dedicated to advanced processes centered on A14. Construction is set to begin in the latter half of 2025, with initial risk production capability in place by the end of 2027, followed by a transition to full commercial mass production starting in late 2028.
Reducing defect density (D0) and improving yield will also be critical for A14. According to reports, development is currently proceeding in line with TSMC's internal targets, and key development milestones toward the 2028 mass-production launch remain on schedule.
A14 Targets Up to 30% Lower Power Consumption Versus N2
A14 aims to further improve on performance, power, and area (PPA) compared with the 2nm process "N2," which entered mass production in the latter half of 2025.
According to figures published by TSMC, A14 delivers 10–15% faster operating speed than N2 at the same power consumption. Conversely, at the same operating speed, it can cut power consumption by 25–30%. Logic circuit density is also expected to improve by more than 20%.
For transistors, A14 will use a next-generation structure that builds on the Gate-All-Around (GAA) nanosheet technology first introduced with N2. By refining structures such as the channel and inner spacers, TSMC aims to suppress parasitic capacitance and improve characteristics during low-voltage operation.
These improvements could translate into better performance for AI processing circuits in smartphone SoCs, as well as reduced power consumption and heat generation in large-scale AI accelerators.
Comparison of TSMC's Advanced Logic Process Specifications
| Process | Transistor Structure | Speed Improvement (Same Power) | Power Reduction
(Same Speed) | Density/Area | Mass Production Start | | ---------- | ------------ | ------------ | ------------ | --------------- | ----------- | | N2 (Baseline) | 1st-Gen Nanosheet GAA | Baseline | Baseline | Baseline | Late 2025 | | A14 | Next-Gen Nanosheet GAA | 10–15% Improvement | 25–30% Reduction | 20%+ Logic Density Improvement | Late 2028 | | A13 | A14-Based Nanosheet | Minor improvement over A14 | Minor improvement over A14 | ~6% Die Area Reduction | 2029 |
To unlock the PPA improvements in A14, TSMC is introducing a standard cell design technology called "TSMC NanoFlex Pro."
With the previous NanoFlex technology, designers could balance performance, power, and area by combining short cells for high density with tall cells for high performance.
NanoFlex Pro takes this flexibility further. Within the same critical path or functional block, designers can now finely mix power-efficient cells with performance-oriented cells.
This makes it easier to concentrate high-performance cells in areas where performance matters most—such as AI compute cores or GPU shaders—while limiting the increase in overall chip area.
Why TSMC Isn't Adopting High-NA EUV for A14
As semiconductor miniaturization pushes into the sub-1nm range, ASML's next-generation lithography system—High-NA EUV (numerical aperture 0.55)—has drawn significant attention.
Intel is moving forward with adopting High-NA EUV systems (the TWINSCAN EXE:5000/5200 series) for its Intel 14A process. TSMC, by contrast, reportedly plans not to adopt High-NA EUV for mass production—at least for the A14 generation—and will continue relying on conventional Low-NA EUV (NA 0.33) instead.
Behind this decision lies not just equipment cost, but broader questions of cost and yield across the entire manufacturing process.
High-NA EUV lithography systems are priced at roughly $350–400 million per unit, far exceeding the roughly $200 million cost of conventional Low-NA EUV systems.
Beyond cost, High-NA EUV also comes with exposure-field limitations rooted in its optical design.
To suppress shadowing caused by increased angles of incidence, High-NA EUV employs an anamorphic optical system with asymmetric magnification—4x in the X direction and 8x in the Y direction. As a result, the area that can be exposed on a wafer in a single pass shrinks from roughly 26mm × 33mm to about 26mm × 16.5mm—roughly half the previous size.
This "half-field" limitation becomes a problem for large chips.
Recent AI accelerators and high-performance GPUs have grown in die size. When a design doesn't fit within a single exposure field, "stitching"—joining multiple exposures together to form one die—may become necessary.
Stitching requires strict control over alignment precision at exposure boundaries. As the process grows more complex, it can increase manufacturing time and reduce yield, ultimately driving up final chip production costs.
Instead, TSMC plans to combine proven NA 0.33 EUV lithography systems with multi-patterning, multiple lithography and etching steps, and circuit layout optimization through Design-Technology Co-Optimization (DTCO).
While this approach may increase the total number of process steps, using equipment and processes with a strong track record in mass production offers the advantage of more predictable yield and manufacturing costs.
If TSMC defers full-scale adoption of High-NA EUV to a generation beyond A14, this could also make manufacturing costs more predictable for major customers like Apple and NVIDIA, who want to keep leading-edge process costs under control.
A13: Shrinking Die Area by About 6% While Reusing A14's Design
TSMC's miniaturization strategy is also reflected in "A13," the derivative process planned to follow A14.
Under the current roadmap, A13 is slated to enter mass production in 2029. While largely inheriting A14's core architecture, A13 will apply an "optical shrink" that reduces linear dimensions to 97%, which is expected to shrink die area by roughly 6% for chips using the same design.
Typically, transitioning to a new manufacturing process requires revising circuit designs and IP, along with re-verification using test chips.
With A13, TSMC is prioritizing design compatibility with A14, aiming to let physical design assets developed for A14 carry over to A13 with minimal changes.
If this works as intended, fabless semiconductor companies could migrate to A13 while keeping redesign costs and timelines low. And with die area shrinking by about 6%, more chips could be produced from the same wafer, potentially lowering the per-chip manufacturing cost.
At a time when performance gains from miniaturization are harder to come by than before, the ability to incrementally improve area and cost while reusing existing designs represents an important advantage for TSMC in encouraging customers to move to next-generation processes.
Diverging 1.4nm-Class Strategies at TSMC, Intel, and Samsung
When it comes to 1.4nm-class advanced processes, TSMC, Intel, and Samsung Foundry are taking noticeably different technical approaches.
Comparing 1.4nm-Class Roadmaps Across Three Leading Foundries
| Foundry | Process | Mass Production Target | Lithography | Transistor Technology | Key Approach |
|---|---|---|---|---|---|
| TSMC | A14 / A13 | 2028 (A14) | |||
| 2029 (A13) | 0.33 NA Low-NA EUV | ||||
| Multi-patterning | Next-gen nanosheet | ||||
| NanoFlex Pro | Leverages proven mass-production technology to prioritize yield and cost; A13 reuses A14's design assets | ||||
| Intel | Intel 14A | 2028–2029 | |||
| Internal products expected in 2027 | 0.55 NA High-NA EUV | Next-gen RibbonFET | |||
| PowerDirect | Adopts High-NA EUV early to reduce lithography steps and mask counts | ||||
| Samsung | SF1.4 | 2029 | |||
| Originally planned for 2027 | Low-NA / High-NA | ||||
| Adoption approach still under review | MBCFET | ||||
| DTCO | Prioritizing improvements to 2nm-generation manufacturing technology and yield first |
Intel is adopting High-NA EUV early for its "Intel 14A" process, aiming to reduce the number of required masks and cut down on certain multi-exposure steps. The company plans to use the technology for its own products starting in the latter half of 2027, before expanding to foundry customers.
However, High-NA EUV brings its own challenges, including equipment cost and the need to work within half-field exposure limits. For large-die chips, the maturity of manufacturing techniques—including stitching—will also matter.
Samsung Foundry, meanwhile, is reportedly prioritizing improvements to its 3nm and 2nm (SF2) manufacturing technology and yield, having pushed back the planned start of SF1.4 mass production from 2027 to 2029.
Rather than rushing to adopt High-NA EUV, TSMC is combining existing EUV technology with DTCO to advance its manufacturing technology incrementally, moving from A14 to A13 step by step.
The key things to watch going forward are the A14 trial production at Baoshan's Fab 20, scheduled for 2027, and the ramp-up of the Taichung Fab 25 mass-production site. The yield, defect density, and mass-production readiness achieved there will likely serve as important indicators of how widely A14 gets adopted in next-generation AI accelerators and smartphone SoCs.