At semiconductor construction sites, the physical speed at which steel frames go up doesn't necessarily match the pace at which fabrication technology matures to shrink circuit linewidths to their limits.
In early September 2026, Taiwanese media reported speculation that "TSMC will pull forward production of its 1.4nm (nanometer) process by a full year, starting in April 2027," and some overseas outlets have covered this with considerable excitement. In the race for leadership in advanced nodes, a one-year gap can appear decisive enough to shift trillions of yen in order share. But a careful cross-check of official announcements from Taiwanese authorities and TSMC's own public statements reveals that this headline conflates distinct stages: building completion, equipment installation and trial runs, and full commercial chip production.
The information originated from an administrative briefing by the management authority of the Central Taiwan Science Park, where TSMC's new fab is located. Authorities confirmed that construction is running roughly half a year ahead of the original schedule. However, TSMC's management has consistently kept its official roadmap for mass production of its most advanced node, "A14," unchanged.
What the Central Taiwan Science Park Authority Revealed About Taichung Fab 25's Construction Progress
According to a report by Taiwan's Economic Daily News (UDN) on September 10, 2026, the Central Taiwan Science Park Bureau confirmed the previous day, September 9, that construction of TSMC's 1.4nm wafer fab (known as Fab 25) in the park's Phase 2 expansion zone has entered a fully accelerated stage. Deputy Director Wang Chun-chieh of the bureau explained to local media that of the four planned fab buildings on the site (P1 through P4), the first building (P1) has already completed its steel-frame assembly and moved on to floor slab and exterior wall construction.
According to the bureau's schedule outlook, construction of the P1 building will be completed in April 2027. Following that, equipment installation and line trial runs (referred to locally as "shiji," or trial machine operation) are scheduled to begin that same month, April 2027. Economic Daily News reported, citing statements from bureau officials and industry sources, that the P1 fab "could reach mass production in the second half of 2027, significantly ahead of the originally planned 2028 start." English-language outlets such as Wccftech expanded on this account, reporting that "TSMC has moved up mass production of its most advanced chips by a full year."
However, this phrase—"mass production in the second half of 2027"—reflects expectations from the administrative bureau and media speculation, not an official statement TSMC has made to investors. According to the bureau, the adjacent second building (P2) is still in the foundation stage, with building completion expected around October 2027. South Korean outlet Asia Business Daily also reported an expected completion of the P2 building within the year.
Some overseas reports have claimed that "P1 and P2 will begin mass production simultaneously in October 2027," but the original Taiwanese report from Economic Daily News only states that the two 1.4nm fabs "could enter production sequentially starting next year"—a staged projection, not a simultaneous launch. While it is true that the overall physical construction schedule has been shortened by roughly half a year compared to the original plan, equating that directly with the start date of commercial wafer shipments involves a logical leap.
TSMC's Official Roadmap Holds Firm on 2028 Commercial Mass Production
In contrast to the pace of construction activity, TSMC's own publicly stated technology development schedule remains notably cautious. At a technology symposium held in North America on April 23, 2025, TSMC unveiled details of its next-generation node, "A14," for the first time. At that event, the company stated that A14 development was progressing well and that yield improvement was ahead of plan, while clearly specifying that it "plans to begin production in 2028."
This stance has not wavered in the company's most recent official announcements. At TSMC's second-quarter 2026 earnings call held on July 16, 2026, Chairman and CEO C.C. Wei reaffirmed that commercial production of the A14 process remains on track to begin in 2028, as previously stated. According to reports from Taiwan's Central News Agency (CNA) and Focus Taiwan, even as fab construction has trended ahead of schedule, management's language regarding the mass-production timeline has not been revised.
During the earnings call, Wei explained that A14 represents the second generation of nanosheet transistor technology and will be produced at a scale even larger than the preceding 2nm (N2) process. The company has also set 2029 as the target for commercial mass production of A13 and A12, nodes more advanced than A14. According to a Q&A summary from the earnings call reported by Taiwanese research firm TrendForce, internal product-like validation shows A14 transistor performance reaching roughly 90% of its design targets.
At the same time, however, Wei cautioned that developing advanced nodes currently takes five to seven years, and that there are no shortcuts. TSMC's official website page introducing A14 technology continues to consistently state, in line with the Japanese-translated wording, that "A14 production is progressing well toward 2028." While government authorities celebrate early building completion, TSMC's own statements make clear that the process itself is bound by physical constraints and rigorous validation cycles.
A14 Node Specifications and the Generational Sequence Following N2
Some overseas media outlets have described A14 as though it were a technology that directly succeeds the current 2nm process. But this differs from TSMC's actual roadmap. In TSMC's official plan, an "A16" process is positioned between N2, the standard 2nm-generation node, and A14, the 1.4nm-generation node.
According to TSMC's published technical information, A16—which introduces backside power delivery technology (BSPDN, branded by TSMC as Super PowerRail)—has been under development with a target production start in the second half of 2026. A14, by contrast, is positioned as a full-node refresh that pushes forward dimensional scaling of transistor structures. Its standard cell architecture introduces "NanoFlex Pro," an evolution of the earlier NanoFlex, giving circuit designers a more granular design environment for balancing performance and power consumption.
- Figures disclosed at 2025 symposium
- Figures disclosed at July 2026 earnings call
データを表で見る
| Figures disclosed at 2025 symposium (%) | Figures disclosed at July 2026 earnings call (%) | |
|---|---|---|
| Max speed increase at same power | 15 | 15 |
| Max power reduction at same speed | 30 | 30 |
| Logic density improvement | 20 | 20 |
In TSMC's April 2025 performance projections for A14 (both compared against its own N2 node), the company cited up to a 15% increase in operating speed at the same power consumption, or up to a 30% reduction in power consumption at the same speed, along with a logic circuit density improvement of over 20%. Notably, the absolute values of operating frequency, power consumption, and transistor density underlying these percentages are not disclosed in the TSMC materials reviewed. At the July 2026 earnings call, the figures Wei presented—10-15% speed improvement at equal power, 25-30% power reduction at equal speed, and roughly 20% logic density improvement—narrowed the initial target ranges to somewhat more realistic figures.
It's worth noting that these figures are not measured data from actual silicon but remain projections based on TSMC's design simulations. Additionally, while some commentary has speculated that Super PowerRail will be broadly adopted in A14, TSMC's official technical pages associate backside power delivery technology with A16 and the future A12 generation, explaining that A14's primary axis of advancement lies in dimensional scaling and the application of the NanoFlex Pro architecture.
The Scale of the $49 Billion Taichung Fab 25
Supporting the realization of this advanced node is the massive complex of buildings under construction in Phase 2 of the Central Taiwan Science Park, known as "Fab 25." According to a roadmap reported by the Taipei Times in July 2025, Fab 25 is a giant complex consisting of four independent fab buildings, P1 through P4.
There is some slight discrepancy between sources regarding the construction start date. Economic Daily News, citing the park authority, reported that groundbreaking occurred in October 2025, while Asia Business Daily reported that TSMC officially confirmed the start of site leveling and foundation work on November 5, 2025. In either case, construction that began in the autumn of 2025 has proceeded at a pace exceeding original expectations.
In response to inquiries from Taiwanese local media, the park authority disclosed that it had received an application from TSMC to build two temporary office structures on the site. These temporary offices are scheduled for completion in April 2027, coinciding with the start of trial operations at the P1 fab, and will house more than 5,400 TSMC operations staff and partner-company personnel who will move in progressively. An additional roughly 1,000 personnel will join once the P2 fab is completed, and by the time all four buildings (P1 through P4) are operational, the site's total workforce is expected to reach between 9,000 and 10,000.
The four fab buildings are being constructed sequentially at intervals of roughly six months. Following completion of the P1 building in April 2027, P2 is expected around October 2027, while P3 has already obtained its building permit and is targeting completion in the second quarter of 2028. P4 is currently in the building-permit application process, with completion expected in the fourth quarter of 2028.
The project's total investment is estimated at approximately NT$1.5 trillion (roughly US$49 billion). While Asia Business Daily reports that TSMC has confirmed the scale of this project, the Taipei Times and other outlets note that the $49 billion figure carries the character of a market estimate. The economic effects expected from such a massive investment are correspondingly significant. According to the park authority's estimates, once all four fab buildings are complete from 2028 onward, annual revenue is projected to exceed NT$500 billion (roughly US$16 billion), creating around 4,500 direct jobs in the region.
The baseline for this construction pace is the original roadmap reported by the Taipei Times in July 2025. Under the original plan, risk production evaluation (trial manufacturing line operation) for the first fab was set to occur within 2027, with full transition to commercial mass production in the second half of 2028 and a monthly capacity target of roughly 50,000 wafers. According to TrendForce, citing Taiwan's Commercial Times, initial construction of the first two buildings (P1 and P2) was awarded to Dahcin Construction and Huju Construction, and as of late July 2026 the pile-driving foundation work was nearly complete, with construction moving on to steel-frame erection. The building shell construction itself is, unquestionably, proceeding smoothly.
A Three-Way Schedule Comparison With Intel and Samsung
Regarding the transition to the 1.4nm generation, comparisons of schedules with Intel and Samsung Electronics—TSMC's rivals in the foundry business—are a perennial focus of investor attention. Organizing each company's stated roadmap alongside the current state of public disclosures clarifies the differences in technological maturity and mass-production timing among the three.
| Foundry and Process | Official Mass-Production Target | Observed Timeline via Reports/Government Statements | Claimed Development Progress | Nature of Supporting Information |
|---|---|---|---|---|
| TSMC A14 (1.4nm-class) | 2028 (officially maintained) | Equipment installation April 2027, mass production possibly in H2 2027 (park authority/local reports) | Internal validation shows ~90% of target transistor performance achieved | Official statements at earnings calls and government briefings |
| Intel 14A (1.4nm-class) | 2028 (high-volume production) | Internal-product risk production expected to begin in H2 2027 | Claims defect density is falling faster than expected | Statements by management at earnings calls |
| Samsung SF1.4 (1.4nm-class) | 2029 (delayed, per reports) | Pushed back from original 2027 plan to 2029; SF1.4 Plus planned for 2030 | Prioritizing yield stabilization of 2nm (SF2/SF2P) | Industry reports and statements at partner events |
Intel has asserted, in its own most recent earnings call, that development of its "Intel 14A" node—equivalent to the 1.4nm class—is progressing well. According to a report by Tom's Hardware, Intel maintains plans to begin risk production for internal products in the second half of 2027, followed by a high-volume manufacturing ramp in 2028.
The company's Chief Financial Officer emphasized that the rate at which defect density is falling for the 14A process exceeds the pace seen during the ramp-up of the company's historically successful 22nm node. However, as Tom's Hardware points out, a falling defect-density trend does not by itself guarantee ultimately high die yields, and it should be noted that the definition of defect classification itself differs between 2010 and today.
Samsung Electronics, meanwhile, has been forced to retreat on its 1.4nm rollout plans. According to reports from South Korean financial outlet The Bell and TrendForce, Samsung has pushed back its commercial mass-production target for SF1.4 from the original 2027 to 2029, in order to concentrate advanced foundry resources on improving yields for its 2nm processes (SF2 and SF2P). Under the plan the company presented at the 2026 SAFE Forum, the improved SF1.4 Plus is now slated for introduction in 2030.
Even when comparing against its two rivals, not a single manufacturer in the world has yet been able to ship 1.4nm-class silicon at this point. What each company is currently competing over is the sophistication of its "announced roadmap"—whether the manufacturing lines actually deliver commercial-grade wafers on a sustained basis will only be revealed by real-world results from 2027 onward.
The Truth Behind the "One-Year Pull-Forward" Narrative, and Metrics to Watch Going Forward
Examining the fundamental time lag in manufacturing between "building completion" and "process qualification" helps bring a clearer picture into focus regarding the series of news reports on accelerated construction at the Taichung fab.
Looking back at how the reporting evolved: as of July 2026, information from Taiwanese media and TrendForce indicated that construction of the first fab's building would be completed by April 2027, with pilot production (trial line operation) possibly beginning as early as the third quarter of 2027, and full mass production coming around mid-2028. Then, following the park authority's routine briefing in September, once the schedule of "equipment installation and trial runs (shiji) in April 2027" was made explicit, some media outlets hastily concluded that this meant "mass production in the second half of 2027—that is, a one-year pull-forward from the original plan."
In ramping up a semiconductor fab, the process from completing the building shell (cleanroom-ready) through equipment installation and piping work, utility connections, and finally trial runs using unprocessed test wafers typically takes several months. The term "shiji" used on the ground in Taiwan refers to the stage of confirming that individual manufacturing tools—such as lithography and etching equipment—operate to specification; it does not mean that a line capable of stably producing commercial chips has been completed.
After equipment trial runs are finished, the "risk production" phase begins, during which circuit pattern defects are identified and the yield curve is pushed up to commercial levels. This process normally requires at least nine months to a year or more. Therefore, if equipment installation and trial runs began in April 2027, it would actually follow a fairly natural semiconductor-engineering timeline for full high-volume manufacturing (HVM) to slip into early-to-mid 2028.
Rather than consuming this reporting as an overly optimistic scoop, several clear checkpoints exist for viewing it as a real industry development.
First is whether construction of the P1 building actually finishes in April 2027 as planned, and whether personnel deployment to the temporary offices and equipment installation begin that same month as announced. Second is whether, at future investor earnings calls, TSMC management explicitly revises its official guidance of "A14 mass production starting in 2028." As long as the official statement on the technology specifications page—that production is progressing well toward 2028—remains in place, the milestone the company has publicly committed to externally remains 2028.
As for the motivation behind rushing physical construction of the fab, one can speculate that it generally aims to secure more time for process adjustments after equipment installation and to reduce uncertainty in the mass-production ramp-up. However, the progress of Taichung Fab 25's construction itself does not, by itself, constitute direct grounds for leapfrogging the technical hurdles of silicon fabrication. Readers of semiconductor news are well served by carefully distinguishing between the speed at which cranes move on a construction site and the speed at which the nanometer world can actually be brought under control.