TSMC is considering manufacturing 3D DRAM, in which memory cells are stacked vertically, The Information reported on November 6, 2026. TSMC has already announced an HBM4 collaboration with SK hynix, but that work centers on manufacturing the logic circuitry that forms the foundation of stacked memory, plus advanced packaging. It does not involve making the memory cells themselves. If the report is accurate, TSMC could become seriously involved in DRAM manufacturing processes.
HBM stacks finished DRAM dies on top of one another, whereas cell-stacked 3D DRAM stacks memory cells inside a single die. Both are three-dimensional structures, but their manufacturing processes are fundamentally different. If TSMC moves ahead with cell-stacked 3D DRAM, it would expand beyond its conventional logic and packaging technologies into the process of forming memory cells. However, no formal market entry or start of mass production has been decided at this point.
Report of a possible entry and options for production sites
According to The Information's report, TSMC may be weighing two options for 3D DRAM production sites: building a new fab, or acquiring and converting an existing one. The start date for production is unknown, and there is no information that a specific capital investment plan has been decided. At this stage, it is best understood that TSMC is exploring the possibility of entry, including securing a production site. The original article from The Information is behind a paywall and we could not review the full text, and as of November 7, 2026, we have not confirmed any official announcement from TSMC itself about entering 3D DRAM.
The term "3D DRAM" refers to different technologies depending on context. In a technical explainer published April 1, 2026 by Tokyo Electron (TEL), a distinction is drawn between 3D DRAM in the broad sense, which includes HBM and other approaches that stack finished DRAM dies, and 3D DRAM in the narrow sense, which forms memory cells three-dimensionally within a single die. The cell-stacked 3D DRAM mentioned in this report falls into the latter category. Confusing it with HBM makes it hard to understand correctly what area TSMC may be moving into.
How does making HBM logic circuits differ from making DRAM memory cells?
The collaboration with TSMC that SK hynix announced on April 19, 2024 includes a plan to use TSMC's advanced logic manufacturing process for the HBM4 base die. The base die is a logic chip placed at the bottom of the HBM stack, with multiple core DRAM dies that store data stacked on top. The stacked dies are electrically connected using through-silicon vias (TSVs). In other words, the base die TSMC would make and the DRAM memory cells SK hynix produces belong to different processes.
The two companies also said they would optimize integration with TSMC's advanced packaging technology, CoWoS. CoWoS is a packaging technology that connects logic chips such as GPUs to HBM through high-density wiring, and a typical configuration is 2.5D packaging using a silicon interposer. This technology also has no direct relationship to the process of forming memory cells inside a DRAM die. Note that the 2024 announcement planned HBM4 mass production for 2026, and that plan should be distinguished from actual production results.
The differences among the HBM4 base die, the HBM stack, and cell-stacked 3D DRAM come down to what is manufactured and in which units things are stacked.
| Item compared | What is made or stacked | Technical position |
|---|---|---|
| HBM4 base die | Logic circuitry forming the foundation of the HBM stack | Subject of the SK hynix–TSMC collaboration; plan to use TSMC's advanced logic manufacturing process |
| HBM | Finished core DRAM dies | Multiple DRAM dies stacked on a base die and connected with TSVs and other means |
| Cell-stacked 3D DRAM | Memory cells inside a single die | Technology that stacks the memory cells themselves vertically in the semiconductor manufacturing process |
This classification is based on SK hynix's collaboration announcement, the TEL explainer mentioned above, and a technical review imec published in 2025. It organizes the differences in what is stacked and in the manufacturing processes involved; it does not compare performance, manufacturing cost, or production status under equal conditions. Nor does it mean that the technologies imec is researching will be adopted by TSMC.
The key point is that TSMC's existing work on logic circuits for HBM4 does not mean it can make cell-stacked 3D DRAM simply by extending that technology. Forming memory cells three-dimensionally requires solving manufacturing challenges that differ from those of conventional logic circuits and HBM packaging. Which materials and cell structures TSMC would adopt has not been made clear.
Stacking memory cells requires transforming the manufacturing process itself
Conventional DRAM holds data in a structure called "1T1C," which combines one transistor and one capacitor. Information is recorded by the presence or absence of charge stored in the capacitor. But as semiconductor scaling advances, it has become harder to shrink the capacitor while maintaining sufficient charge retention. imec's technical review also points out that capacitor dimensions and leakage current limit DRAM density and data retention time. Because stored charge is lost over time, data must be periodically rewritten through refresh operations, and the power consumed by that process is not negligible.
One approach being researched to overcome these constraints is monolithic 3D DRAM, which stacks cells vertically instead of shrinking them further on a flat plane. Rather than stacking finished chips as HBM does, it forms memory cells across multiple layers within the semiconductor manufacturing process. This could increase storage capacity per unit area, but it requires manufacturing multiple layers of transistors and stabilizing the electrical characteristics of each. Being able to form a three-dimensional structure and getting it to operate stably as practical memory are separate challenges.
One technology imec is studying is a "2T0C" structure that uses the oxide semiconductor IGZO (indium gallium zinc oxide). Unlike conventional 1T1C, it uses two thin-film transistors, one for reading and one for writing, and omits a separate storage capacitor. However, the capacitance needed to hold charge does not disappear entirely. Data is stored using the parasitic capacitance present in the read transistor, which calls for a cell design different from that of conventional DRAM.
One advantage of IGZO is that thin-film transistors could potentially be formed at relatively low temperatures. This opens the way to building memory cells into the back-end-of-line (BEOL), the wiring-formation stage of semiconductor manufacturing. Using this property, imec is researching structures that place memory arrays on top of peripheral circuits and technologies that stack memory cells in multiple layers. If memory layers can be formed on top of existing circuits, it may be possible to raise storage density without relying solely on lateral scaling.
However, imec's review lists the reliability of IGZO transistors as a key challenge. A particular concern is PBTI (positive bias temperature instability), in which characteristics change under the influence of positive gate voltage and temperature. This phenomenon can cause the transistor's threshold voltage to shift or its drain current to decline. Even if high-density cells can be formed, DRAM cannot be practical unless the characteristics of the transistors handling reading and writing remain stable over the long term. These are research challenges published by imec and do not indicate that TSMC will adopt IGZO or 2T0C.
Inspection and handling of defects also become harder once memory cells are stacked. An explainer by Motoaki Ito published on the TEL site points to the difficulty of inspecting and repairing intermediate layers in a stacked structure. It is not enough to be able to form each layer; defective cells and layers must be identified, and the chip must be brought to a state usable as a product. If yield, the proportion of manufactured chips that can be shipped as good products, is low, manufacturing costs balloon and the profitability of mass production suffers.
Production plans and stable supply capability will be key to judging TSMC's entry
If TSMC moves into manufacturing cell-stacked 3D DRAM, its business could expand from supplying logic circuits in existing HBM collaborations to making the part that stores data. However, the business model remains unclear, including which company would design the memory and who would manufacture it. Whether TSMC would contract-manufacture DRAM designed by others, as in its conventional foundry business, or go as far as selling its own products would greatly change its relationship with existing memory makers. If it is contract manufacturing, collaboration with existing companies could expand, and it would not necessarily lead directly to competition with SK hynix, Samsung Electronics, or Micron.
AI memory also requires more than large storage capacity. Memory bandwidth to feed large amounts of data quickly to processors such as GPUs, and the packaging technology that connects memory to compute chips, are also important. Even if cell-stacked 3D DRAM raises storage density, that alone does not improve the performance or supply capacity of HBM as a whole. The report contains no information on the start of mass production, production capacity, or specific product specifications, so there is no basis to conclude that it will ease near-term memory shortages or improve PC DRAM prices.
Evaluating the impact of TSMC's entry on the semiconductor industry will require a formal business policy, along with the cell structure, manufacturing process, product specifications, and mass-production schedule it would adopt. Whether it can secure yields suited to its production scale and supply good products reliably will also be an important factor. If these conditions are met, TSMC would expand its role from a supplier of the logic circuits and packaging technology that support memory to a company that manufactures the memory cells themselves.