TSMC has disclosed in a research abstract a technology that shrinks the SRAM cell area to below 0.017µm² on A14, its next-generation semiconductor manufacturing process scheduled for mass production in 2028. The company plans to present the work on December 14 at the International Electron Devices Meeting, IEDM 2026, and says overall SRAM circuit density will also reach a record high.
SRAM is used in logic chips such as CPUs and GPUs as cache memory, which handles high-speed data access. Cell area refers to the area of the basic circuit that stores one bit, while SRAM macro density expresses how much storage capacity fits in a given area, including peripheral circuits. A14 will push SRAM cell scaling further, but the view that "roughly eight years of stagnation has been broken" needs some qualification. TSMC also reported a 0.0199µm² cell in its 2022 3nm research, so the new result should be assessed with earlier research figures and differences in application in mind.
The "Eight-Year Stagnation" Has a 2022 Exception
As early as 2022, TSMC announced research results for a high-density SRAM cell below 0.021µm². Paper 27.1, included in the IEEE's official IEDM archive, reports achieving 0.0199µm² using 3nm CMOS technology. The abstract at the time positioned it as the smallest high-density SRAM cell area reported to that point.
The paper, by Chih-Hao Chang and colleagues, is titled "Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond." The abstract also notes that a 256Mb SRAM macro was actually operated and verified. In other words, it was a research result backed by operational verification, not merely a future target. That said, this figure cannot simply be treated as a cell specification common to all production products.
South Korea's ETNews reported on October 26 that the SRAM cell, which measured 0.021µm² on the N5 process in 2020, will shrink again with A14 in 2028. The "roughly eight years" here refers to the span from 2020 to 2028, the planned start of A14 mass production. It does not mean eight years have already passed as of 2026.
The broad trend of SRAM cell scaling effectively stalling around 0.021µm² is not inconsistent with the existence of a research example that achieved a small reduction in 2022. However, it would not be accurate to interpret this as cell area never changing in any research during that period. The sub-0.017µm² figure shown for A14 is also below the 2022 figure of 0.0199µm². Even accounting for past exceptions, the significance of the result, a further step in SRAM cell scaling, does not change.
Comparing Published Research Figures Over Time
Looking back at the research TSMC has published, the 2022 3nm research showed 0.0199µm², the 2025 introduction of N2 research showed 0.021µm², and the A14 abstract released in 2026 shows a value below 0.017µm².
| Year / Source | Research subject / scope | SRAM cell area | Caveats for comparison |
|---|---|---|---|
| 2022 – IEDM research abstract | 3nm CMOS high-density SRAM research | 0.0199µm² | A value reported in research, not a specification common to production products |
| 2025 – TSMC research introduction | N2 high-density SRAM bit cell | 0.021µm² | A different design from 2022; does not indicate a technical step backward for N2 as a whole |
| 2026 – IEDM published abstract | A14 SRAM cell | Below 0.017µm² | 0.017µm² is an upper bound; actual area not disclosed. Mass production planned for 2028 |
These figures differ in publication timing and research subject, and they are not the result of comparison under identical conditions. Because they are lined up without accounting for differences in application and design, they do not show that SRAM cells have shrunk consistently as production process generations advanced.
With that in mind, let's calculate the reduction rate by assuming A14's cell area is 0.017µm². The formula is (1 − 0.017 ÷ comparison cell area) × 100. Compared with 0.021µm², it equals an area reduction of about 19%; compared with the 0.0199µm² reported in the 2022 3nm research, about 15%.
However, the value TSMC published is "below 0.017µm²," so 0.017µm² is not the actual cell area. If the actual area is smaller, the reduction would exceed these calculations. Also, the roughly 19% and 15% figures are simple calculations using published values from different designs, not reduction rates between product generations measured under identical conditions. Nor are SRAM macro density, including peripheral circuits, or production yield necessarily going to improve by the same proportion. Evaluating A14's technical progress in terms of actual products requires comparisons with matched applications and operating conditions.
Even at 3nm, SRAM Cell Area Varies by Application
TSMC's 2025 research list also includes a different SRAM using the same 3nm technology with a cell area of 0.052µm². This is research on a "dual-port SRAM," which has two access ports. Because its application and circuit configuration differ from the high-density SRAM cell reported in 2022, the two cannot be compared on the shared "3nm" process name alone.
This dual-port SRAM reportedly achieved 3.6GHz operation at 1.0V, with a minimum operating voltage of 495mV. The key point is that 3.6GHz was obtained at 1.0V; it does not mean the same speed is achieved at 495mV. Evaluating SRAM performance requires checking not only cell area but also how much speed can be reached at what voltage.
Therefore, the 0.052µm² figure alone is not grounds for judging it technically inferior to the high-density SRAM cell. Likewise, the fact that the 2025 N2 high-density SRAM cell is 0.021µm², larger than the 0.0199µm² of the 2022 3nm research, does not indicate a technical regression for N2 as a whole. A shared or newer process generation name does not mean SRAMs of differing applications and designs can be compared on the same basis.
In fact, TSMC's official research introduction for N2 explains that, while using a 0.021µm² cell, it raised SRAM macro density to 38.1Mb/mm². That is 1.1 times the previous generation, achieved by co-optimizing design and manufacturing technology. The area of a single cell and the storage capacity that fits in a whole SRAM macro including peripheral circuits are different metrics. Even when scaling the cell itself becomes difficult, room remained to raise SRAM macro density through circuit design improvements.
What to Watch: Operating Conditions and Overall SRAM Circuit Density
The published A14 abstract says chip density improves by about 20% compared with N2. This comes from scaling in both logic and SRAM, and does not mean a 20% improvement in SRAM density alone. Still less does it mean CPU or GPU performance rises 20%. How much cache capacity can actually be increased in real products cannot be judged from the sub-0.017µm² cell area alone.
Although TSMC claims to have achieved record SRAM macro density for A14, the published abstract gives no specific figure. Operating voltage and production yield are also not known at this point. The 2028 date refers to the planned start of mass production on the A14 process and does not guarantee that CPUs or GPUs using the technology will be released that year.
The next thing to watch is how much the December 14 IEDM 2026 presentation reveals about specific SRAM macro density figures and operating conditions. What applications the shrunken cell will serve, at what voltage and speed it operates, and how much storage capacity fits per unit area including peripheral circuits: once these conditions are clear, it will be possible to evaluate more concretely what A14's scaling means for future CPU and GPU cache design.