TSMC, facing tight capacity for advanced packaging used in AI semiconductors, is cooperating with external OSATs to boost supply. Taiwan's Central News Agency reported on July 12 that, against the backdrop of the CoWoS shortage, order opportunities are expanding for Intel's EMIB as well as for Advanced Semiconductor Engineering (ASE), Siliconware Precision Industries (SPIL), and Powertech Technology (PTI). However, the names and volumes of customers that have shifted to Intel have not been disclosed. Nor has it been officially stated that the CoWoS shortage is the reason behind EFB, which AMD is developing together with Taiwanese firms. Separating out process outsourcing—where TSMC retains control—from design migrations to alternative packaging schemes reveals the true nature of the business opportunities each company is capturing.
TSMC Itself Has Acknowledged the CoWoS Shortage
At the Q1 2026 earnings call held on April 16, TSMC CEO C.C. Wei acknowledged that the company's advanced packaging capacity is "very tight." He explained that meeting customer demand requires cooperation with OSATs (outsourced semiconductor assembly and test companies). While TSMC is also expanding its own capacity, it remains insufficient by his own account. This expansion of outsourcing is not merely speculation born from secondary reporting.
TSMC has not disclosed the absolute size of the supply-demand gap. On June 15, the Economic Daily News reported, citing institutional investor estimates, that the CoWoS supply shortage could shrink from around 20% at the time to around 10% by the end of 2026. While these figures are external estimates rather than company plans, they suggest that even factoring in rapid capacity expansion, the shortage will not disappear within the year.
On the demand side, the area consumed per package is also growing. TSMC is currently producing CoWoS packages equivalent to 5.5 times the area that a single reticle of an exposure tool can draw in one shot. The company plans to expand this to 9.5 times by 2027 and 14 times by 2028, with the 14x version designed to integrate roughly 10 large compute dies and 20 HBM (high bandwidth memory) stacks. Even as the number of units produced increases, the package area and process load per product simultaneously balloon. This is why expanding capacity alone struggles to resolve the shortage.
Three Layers: Process Outsourcing, Alternative Schemes, and Customer Migration
The "ripple effect on orders" splits into three categories based on differences in business flow and technology.
| Work Moving Outside | Representative Example | Party Controlling Design/Customer Relationship | Competitive Pressure on TSMC |
|---|---|---|---|
| Process outsourcing under TSMC's scheme | Orders to Amkor for advanced packaging and testing services | TSMC leads turnkey supply | Small. Functions as capacity expansion |
| Qualification and mass production under alternative schemes | AMD's EFB with ASE, SPIL, PTI | Chip design companies and OSATs | Moderate. An alternative market grows for each use case |
| Customer migration to a competing scheme | Cases of moving CoWoS-candidate designs to Intel's EMIB-T | Intel and the customer | Large. However, disclosed major cases remain limited |
In the first flow, TSMC continues to hold the contract with the customer and control the process design, while entrusting part of the back-end process to an OSAT. Even though a portion of revenue flows outward, TSMC's 3DFabric ecosystem and turnkey supply capability are strengthened. The 10-year agreement TSMC and Amkor signed on June 16 fits this pattern. The two companies are expanding capacity in Arizona, establishing a framework under which TSMC procures advanced packaging and testing services from Amkor.
The second and third flows are different in nature. Changing the packaging scheme requires redesigning the interconnects between dies and the substrate configuration. Power delivery and heat dissipation also change, requiring re-qualification that includes warpage and inspection methods. This is not something that can be switched simply by moving the same unfinished wafer to an available fab. Customers must incorporate a second supply chain at an early design stage and repeat prototyping and yield verification. Companies that achieve qualification here are more likely to remain in the supply chain even after TSMC's capacity expansion.
How Far Can Intel's EMIB-T Serve as an Alternative?
Intel's EMIB (Embedded Multi-die Interconnect Bridge) differs from schemes that cover the entire package with a large silicon interposer. Instead, it embeds small silicon bridges only where high-density wiring is needed. EMIB has been in mass production since 2017, and in 2025 Intel introduced EMIB-T, which adds TSV (through-silicon vias) to the bridge to enhance power delivery and bandwidth scalability. 2026 will be the year to test whether this technology can be moved into mass production for external customers.
Technical preparations are advancing. At ECTC (Electronic Components and Technology Conference) 2026, Intel explained that EMIB-T's first-layer connection pitch has been narrowed to 25 micrometers, enabling integration of compute and memory silicon exceeding nine times the reticle area within a package up to 120×120 millimeters. In its Q4 2025 earnings materials as well, Intel stated it is improving quality and yield for customers hoping for a launch in the second half of 2026.
On the other hand, commercial track record is not as clear-cut as the technical materials suggest. In its 2025 annual report, Intel stated that external foundry customers currently remain "few." The Central News Agency report likewise did not disclose the names of customers that shifted to Intel, order values, or mass production volumes. What can be confirmed, therefore, is only that EMIB-T is emerging as a strong candidate for absorbing the CoWoS shortage, and that customers are considering mass production in the second half of 2026. It cannot yet be said that major customers have broadly migrated.
TSMC, too, is countering with larger package sizes. Intel's announcement states that EMIB-T can accommodate compute and memory silicon totaling over nine times the reticle area. Meanwhile, TSMC's figures of 5.5x, 9.5x, and 14x represent the reticle scale of CoWoS packages. Since the targets differ, these multipliers cannot be directly compared to determine superiority. Local bridges versus full-coverage or molded interposers differ in structure and in the products they suit best. What determines the winner is not the maximum area, but whether a scheme can satisfy the required number of HBMs and bandwidth while achieving mass production at acceptable cost and yield.
Taiwan's OSATs Are Capturing the Immediate Real Demand First
In terms of near-term orders, it is Taiwan's OSATs—not Intel—that are ahead. On May 21, AMD announced plans to invest over $10 billion in Taiwan's semiconductor and system supply chain, stating that it would co-develop and qualify wafer-based 2.5D EFB (Elevated Fanout Bridge) together with ASE and SPIL. With PTI, AMD has already qualified a panel-based 2.5D EFB, citing it as a technology supporting the next-generation EPYC "Venice."
EFB is not simply about borrowing available CoWoS capacity as-is. It represents an effort by AMD, tailored to its own chiplet designs, to build a separate 2.5D bridge supply chain across multiple OSATs. By qualifying wafer-based and panel-based approaches in parallel, AMD can choose capacity, cost, and supply region on a per-product basis. A division of labor is spreading in which advanced logic is manufactured at TSMC while back-end processes adopt non-TSMC schemes.
From the outside, TSMC's contract with Amkor and AMD's EFB with Taiwanese OSATs might both look like the same kind of "outsourcing." But the former extends TSMC's own service capacity outward, while the latter sees design companies cultivating an alternative scheme. OSAT companies can capture work from both. What poses a genuine competitive threat to TSMC is not the sheer volume of outsourcing, but how many generations the latter's qualified designs endure.
Three Numbers to Watch Through 2027
The first is the number of mass-production customers and order scale that Intel can disclose. Even if EMIB-T's maximum dimensions and connection pitch are superior, if the second-half-2026 launch remains confined to anonymous prototypes, its power to erode CoWoS's market dominance will be weak. Conversely, if customer names and mass production timing emerge for HBM-intensive AI ASICs, Intel's advanced packaging business will gain a breakthrough toward expanding its external foundry footprint.
The second is the actual trajectory of the CoWoS supply-demand gap said to be shrinking from around 20% to around 10%. If TSMC's capacity expansion combined with process outsourcing to OSATs moves the shortage toward resolution, the incentive to rush toward competing schemes will weaken. Even so, a qualified second supply chain will likely remain as insurance against geopolitical risk and sudden demand surges.
The third is the yield and introduction timing of large-scale packages. A key inflection point will be whether TSMC's 9.5x CoWoS launches on schedule in 2027, and whether Intel can mass-produce 120×120 millimeter-class EMIB-T in customer products. In the near term, it will be worth checking whether new details on advanced packaging capacity expansion and OSAT division of labor emerge at TSMC's Q2 earnings call on July 16. Whether this ripple effect on orders ends up being a temporary measure to handle congestion, or becomes established as a new, lasting supply chain, will be determined once customer names, mass production volumes, and yield figures all come together.