TSMC CoWoS Prices Reportedly Set to Rise Up to 20% as AI Chip Demand Strains Packaging Capacity

The growing size of AI chips is straining advanced packaging capacity. On October 27, 2026, Taiwan's Commercial Times (工商時報), citing supply chain sources, reported that quoted prices for TSMC's advanced packaging technology "CoWoS (Chip-on-Wafer-on-Substrate)" could rise by as much as 20%. The paper also said price adjustments of 10–20% are under discussion across the broader industry, including foundries and OSATs (outsourced semiconductor assembly and test companies). This does not mean, however, that TSMC has decided on a uniform 20% increase for all customers. The company has not officially announced a price revision, and the timing, the technologies covered, and the conditions for applying it to long-term contracts remain unclear. Based on this report, we look at why advanced packaging has become a supply bottleneck and at the situation surrounding competing technologies.

CoWoS Prices Up to 20% Higher? Separating the Report From Confirmed Facts

The Commercial Times report rests on the accounts of anonymous supply chain sources and describes a possible increase in quoted prices. The paper says an increase of up to 20% is being discussed for TSMC's CoWoS, while separately noting a view that the wider foundry and OSAT industry is also considering price adjustments of 10–20%. The two figures refer to different scopes, and TSMC has not decided to raise prices uniformly on every CoWoS product. Nor do the published materials we could confirm show the current prices used as the baseline for the increase, or the prices after any revision. TSMC has offered no official explanation of the speculation, so details including contract terms and timing should be treated as unconfirmed.

The report also does not go into specific contract terms. CoWoS pricing probably varies with customers' order volumes, their long-term capacity reservations, package area, and the technology variant used. Yet the report does not disclose when any increase would take effect, which customers it would cover, what the baseline price is, or which regions are included. Where large customers have fixed pricing terms in long-term contracts, a revision of quoted prices for new orders would not necessarily flow through to existing contracts immediately. Nothing confirms that customers have accepted a price increase request.

In the semiconductor industry, when supply becomes tight, manufacturers sometimes ask customers to revisit quoted prices and contract terms. Such negotiations can serve purposes such as curbing excess orders, encouraging long-term contracts, and securing funds for capital investment. The "up to 20%" figure is therefore best read not as a confirmed rise in transaction prices, but as a signal that surging demand for AI chips is tightening the supply of advanced packaging.

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Larger AI Chips and More HBM Stacks Strain CoWoS Capacity

Behind the price speculation is the steadily growing complexity of AI accelerators. TSMC's CoWoS is a 2.5D packaging technology that places multiple logic dies and high-bandwidth memory (HBM) in a single package and connects them with high-density wiring. CoWoS is not a single manufacturing method, however; it splits into several technologies depending on the structure of the interposer that connects the dies.

The oldest, CoWoS-S, uses a silicon interposer. Because fine wiring can be formed on silicon, high connection density is easy to achieve, but making the interposer larger involves manufacturing constraints. According to TSMC's technical materials, CoWoS-S supports up to about 2,700 square millimeters, roughly 3.3 times the reticle size of lithography equipment, and TSMC says CoWoS-R or CoWoS-L is better suited to larger packages.

CoWoS-R connects dies through a redistribution layer (RDL) made of organic material, and mass production was announced for 2023. CoWoS-L, meanwhile, combines an RDL with localized silicon bridges (LSI), providing high-density wiring only where needed while enlarging the whole package. Mass production of a 3.5x-reticle configuration began in 2024, and further enlargement is under way. Unlike CoWoS-S, which uses a silicon interposer across the whole area, placing silicon bridges only where needed makes the structure easier to scale to large areas.

Equipment makers and industry sources interviewed by the Commercial Times point out that larger AI chips are reducing the number of products that tools can process in a given time. With a large-area silicon interposer, for example, the larger the area, the fewer units can be made from a single wafer. The process of precisely placing and bonding multiple logic dies and many HBM stacks is also more complex. As packages grow, warpage caused by differences in the thermal expansion of materials becomes harder to control, raising the risk of bonding defects. Finished products may also require more inspection items and longer test times as connection points multiply and structures become more intricate. These factors combine to burden both the packaging and testing stages, the sources say.

Detailed data such as actual product mix, manufacturing cycle times, defect density, and the number of tools in operation has not been made public, however. It is therefore difficult for outsiders to calculate precisely by what percentage capacity has fallen because of larger packages. Even so, as AI chips become larger and denser, the manufacturing and inspection resources needed per finished unit may increase, and supply capacity can no longer be judged by tool additions alone.

A New Plant Takes About Three Years, and Equipment Lead Times Are Lengthening

Increasing supply requires building new plants or expanding equipment, but advanced packaging lines cannot be stood up quickly. Industry sources interviewed by the Commercial Times say it takes about three years from groundbreaking until equipment for the main processes is fully operational at an advanced packaging plant. Even after the building is finished and tools are installed, cleanroom conditions must be adjusted, manufacturing conditions optimized, and yields verified with customer products. Capacity does not reach its planned level the moment equipment is installed.

Procurement lead times for manufacturing equipment are also getting longer. According to the paper, equipment delivery lead times have stretched from the previous 3–6 months or so to 6–8 months. Equipment makers themselves face constraints in sourcing critical components, so even if foundries increase capital spending, they may not be able to secure the tools they need right away. In other words, there are supply constraints that money alone cannot resolve.

Outside analysts and research firms have forecast that TSMC's monthly wafer processing capacity for CoWoS will exceed 130,000 wafers in 2026 and reach 200,000 in 2027. There are also reports that the advanced packaging plant "AP1," planned in the United States, will begin operating in 2028. These capacity figures and timelines are external estimates and forecasts, however, not numbers or schedules TSMC has officially committed to. Nor can monthly wafer throughput be converted directly into the number of finished packages shipped. With methods that use large interposers, the number of parts obtainable from one wafer falls as package area grows to 5 reticles, 9 reticles, and beyond.

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TSMC itself acknowledges the shortage of advanced packaging supply. At its third-quarter earnings call on October 15, 2026, Chairman and CEO C.C. Wei said there is a "very large" gap between demand and supply for advanced packaging, including CoWoS. He did not specify the size of the shortfall or when supply and demand would balance.

TSMC has kept its 2026 full-year capital expenditure plan at $60–64 billion. But not all of it goes to expanding CoWoS capacity; most of the investment is directed to manufacturing equipment for advanced logic chips. The 13 new plants reportedly under construction in Taiwan also combine advanced logic fabs and advanced packaging facilities, so not all of them bear directly on CoWoS output. Assessing future supply capacity requires looking not only at total capital spending but also at how much goes to advanced packaging and at the ramp-up status of each plant.

CoWoS From 5.5 to 14 Reticles: Mass-Production Technology vs. Future Plans

When assessing advanced packaging supply, it is important to distinguish technologies already in mass production from those still aimed at future deployment. The roadmaps companies publish include not only current manufacturing capability but also development targets several years out. For package enlargement in particular, being able to build something is not the same as being able to mass-produce it with sufficient yield.

At the October 15, 2026 earnings call, TSMC's Wei said 5-reticle packages are in volume production with "excellent" yields. Materials the company presented at its 2026 North America Technology Symposium, meanwhile, say 5.5-reticle CoWoS is in production. Whether the difference stems from measurement standards or from individual customers' designs and product configurations is not clear. The 5x and 5.5x figures therefore cannot be treated as exactly the same mass-production specification, but it is confirmed that TSMC is already building packages of this scale.

TSMC is also developing 9-reticle and 14-reticle CoWoS. According to the symposium materials, 14-reticle CoWoS is scheduled to begin mass production in 2028 and is envisioned to carry about 10 large compute dies and 20 HBM stacks in a single package. Larger packages beyond 14 reticles are slated for 2029 and later. These are future development and production targets, however, and cannot be counted in current supply capacity.

Another technology drawing attention for its potential to cut manufacturing costs is "CoPoS (Chip-on-Panel-on-Substrate)," which TSMC is researching. It aims to reduce costs by using large rectangular panels instead of round wafers, improving the utilization of substrate area. Wei describes CoPoS as R&D aimed at future cost reductions. Volume shipments have not begun, and there is no demonstrated record of it actually lowering existing CoWoS manufacturing costs.

It is also worth noting that the high yields and competitive advantages TSMC describes are the company's own assessments. No independent third-party yield measurements or head-to-head comparisons with competing technologies under identical conditions have been published. Even if package areas on the roadmap grow, how far actual manufacturing costs, supply capacity, and production stability will improve remains to be seen.

Can Intel's EMIB Substitute for CoWoS? Technology and Ecosystem Barriers

As concerns grow over CoWoS shortages and price increases, Intel's "EMIB (Embedded Multi-die Interconnect Bridge)" has drawn attention as an alternative. CoWoS and EMIB share the goal of connecting multiple semiconductor dies at high density, but their structures differ. Some argue that EMIB is difficult to scale to large HBM-equipped configurations, but given the state of technology development Intel has disclosed, that is not necessarily an accurate assessment.

According to Intel's technical materials, EMIB embeds small silicon bridges inside an organic package substrate to connect adjacent dies. Because it does not need a large silicon interposer covering the entire package, it can scale up in size while limiting the silicon area used. Intel has used EMIB in commercial products since 2017 and has a track record of volume shipments.

In March 2026, Intel also announced that "EMIB-T," which adds through-silicon vias (TSVs) to the silicon bridge, will support scales beyond 6 reticles. EMIB-T is positioned as supporting not only connections between logic dies and HBM stacks but also vertical power delivery. Although we could not confirm large-scale commercial shipments, it would not be appropriate to regard EMIB as a technology usable only for small die-to-die connections. Intel's packaging roadmap, published in March 2026, also aims for a die-complex area of more than 8 reticles (about 6,800 square millimeters) in 2026 and more than 12 reticles (about 10,000 square millimeters) by 2028.

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Still, being technically able to scale up is a separate matter from customers being able to switch easily from their existing packaging technology. TSMC's CoWoS benefits from years of volume-production experience and an ecosystem that supports everything from chip design to manufacturing and testing. This established development and manufacturing base is one factor making migration to a competing technology difficult.

Major GPU makers such as NVIDIA, and cloud providers developing their own AI ASICs, have built design flows, physical IP, HBM connection configurations, and inspection methods premised on CoWoS. Moving to a different packaging technology could require changes to die-to-die connection structures and package substrate design, re-evaluation of electrical and thermal characteristics, and qualification of manufacturing processes. For some products, such work could take six months to a year or more and delay market launch. In the AI chip market, the timing of new product introductions bears directly on competitiveness, so the decision to switch cannot be made on packaging cost savings alone. Even if CoWoS prices rose 10–20%, continuing with existing technology may be more rational once design-change costs and the risk of delivery delays are taken into account.

That said, such switching costs do not guarantee CoWoS's advantage permanently. If the shortage drags on and customers cannot secure the volumes and delivery dates they need, moves to consider Intel's EMIB or technologies offered by other OSATs as alternative manufacturing routes could strengthen. For newly designed products in particular, there is room to compare multiple packaging technologies from the early stages of development. At present, however, no objective data has been published comparing CoWoS and EMIB on price, qualified production capacity, volume yield, and lead time using the same customer design. Which is more advantageous depends not only on package structure but also on individual product requirements, production capacity, and existing design assets.

How Much Would a CoWoS Price Hike Affect AI Chip Prices?

If CoWoS prices were raised, the effect could extend to end-product prices. But an increase in packaging costs does not translate directly into the same percentage increase in the price of AI accelerators or AI servers.

The manufacturing cost of an AI accelerator includes wafer fabrication for advanced logic chips, HBM procurement, and packaging and testing. For a whole AI server, costs for boards, power supplies, cooling systems, and networking equipment are added on top. Even if CoWoS manufacturing costs rose 20%, the effect on the accelerator's total cost would depend on the share packaging accounts for. Whether chipmakers absorb the increase through lower margins or pass it on to customers in sales prices will also depend on individual contract terms and the competitive environment.

It is therefore not possible to predict, on this report alone, a sharp rise in consumer GPU prices or product shortages across the semiconductor market. What matters more is how far equipment expansion and yield improvements can keep pace with the growing size and density of AI chips. Capacity should be evaluated not just by wafer throughput but also by finished-product shipment volumes and the time required for manufacturing and testing.

The key questions going forward are whether TSMC actually implements a CoWoS price revision and whether capacity expansion can keep up with demand growth. The allocation of capital spending to advanced packaging, the start-up timing of new plants, equipment delivery lead times, and progress in improving volume yields will be important indicators. Attention will also be on whether commercial AI chips using competing technologies such as Intel's can build a stable record of volume production in both performance and supply.

The reported price increase of up to 20% has not been confirmed at this point. Still, the underlying issues, the growing size of AI chips and the supply constraints in advanced packaging, are challenges TSMC itself acknowledges. Going forward, it will be necessary to keep watching not only for official announcements on price revisions but also for the production status of next-generation packaging technologies and improvements in supply capacity.