For TSMC's 2nm process "N2," customer design adoption is spreading at a pace that outstrips previous generations. At the TSMC 2026 Japan Technology Symposium held in Yokohama on July 3, Senior Vice President and Deputy Co-COO Kevin Zhang revealed that the number of N2 tape-outs in its second year had reached four times that of N3 at the same stage. Meanwhile, in the Q2 2026 earnings TSMC announced on July 16, N2's wafer revenue share stood at 3%. Between the completion of design data and mass-production revenue lies a long process involving manufacturing lead times, yield, and product launch timing. What the fourfold figure indicates is not the volume of finished products shipped, but a thickening pipeline of future production candidates.
Fourfold Is a "Design Completion Count," Not a Revenue Multiple
A tape-out refers to the milestone at which a semiconductor's circuit layout is finalized and handed off for photomask production and the prototyping/mass-production process. A single tape-out does not correspond to a single company—the same customer may run multiple products, dies, or design revisions through the process. Therefore, from the explanation that N2's tape-out count is four times that of N3, one cannot conclude that the number of customers or wafer starts has quadrupled. The same holds true for order value and shipment volume.
This statement was a relative comparison between N2's second year and the equivalent stage for N3. DIGITIMES and MONOist, which covered the Japan event, reported the fourfold figure, but the absolute tape-out counts for N2 and N3, product mix, and how test chips or design revisions were counted have not been disclosed. Rather than treating this as a reproducible statistic, it is more appropriate to view it as an indicator of adoption pace that TSMC presented at a customer event.
Even so, this represents an advance over previous outlooks. At its January 2025 earnings briefing, TSMC had indicated that the number of tape-outs expected in the two years following N2's mass-production launch would exceed those of both the N3 and N5 generations. This latest statement adds a sense of scale—"four times N3"—to that trajectory. Semiconductor Engineering, covering TSMC's April 2026 North American Technology Symposium, also reported that TSMC had explained it had received more than 20 N2 tape-outs, with more than 70 in the pipeline. Whether this counting scope matches the fourfold figure cited in Yokohama cannot be confirmed, but it can be read that multiple design projects are progressing as mass-production candidates. The number of customers and per-customer counts remain unknown.
The timing of conversion to mass-production revenue varies by customer. In April 2024, TSMC CEO C.C. Wei explained that, given wafer manufacturing cycle times and back-end processes, N2's mass-production ramp would resemble that of N3. Tape-outs and product launches are also influenced by each company's roadmap and business decisions. While an increase in design projects expands future revenue opportunities, small mobile dies and large server CPU dies differ in both required wafer volume and selling price.
GAA and NanoFlex Broadened Design Options
N2 is the first TSMC-manufactured advanced logic process to adopt Gate-All-Around (GAA) nanosheet transistors. In the FinFET structure used through N3, the gate covers a fin-shaped channel from three sides. With GAA, the gate surrounds a thin nanosheet on all sides, enhancing current control. Compared with N3E, TSMC touts a 10–15% speed improvement at the same power, a 25–30% power reduction at the same speed, and more than 15% greater chip density.
Supporting this design flexibility is a mechanism called "NanoFlex." It allows short standard cells that prioritize area and power efficiency to be combined with tall standard cells that prioritize speed, within the same design block. This enables adjustments such as placing high-performance cells along timing-critical paths in a CPU core while using compact cells around caches and control circuitry. The ability to vary the allocation of performance, power, and area by location within a product—rather than using N2 with a uniform performance setting—broadens the range of adoption.
Even with the process ready, tape-outs are unlikely to increase without design tools and validated IP in place. In April 2025, Cadence announced that its digital design, custom/analog design, and thermal analysis flows had been certified for N2P and A16. It also said it had prepared DDR5 12.8G IP for N2P. By having TSMC, EDA companies, and IP providers establish the design foundation early, customers can more easily contain the verification burden that comes with transistor structure changes.
At its April 2026 earnings briefing, TSMC explained that N2 entered mass production with good yields in Q4 2025, and that there is strong demand from both smartphones and HPC/AI. Mobile SoCs emphasize power efficiency, while data-center CPUs emphasize computational performance and power density. Combining publicly available materials, one can infer that the breadth of design adjustment enabled by NanoFlex, the readiness of design tools and IP, and the roadmap of derivative processes together formed the foundation supporting adoption. However, TSMC has not disclosed the fourfold breakdown by application or by process, so individual factors cannot be directly tied to specific counts.
What a 3% Wafer Revenue Share and AMD's Venice Reveal About the Substance of Mass Production
In Q2 2026, N2 accounted for 3% of TSMC's wafer revenue. In the same quarter, N3 accounted for 30%, N5 for 33%, and N7 for 11%, with advanced processes of 7nm and below together accounting for 77%. This was the first time N2 was disclosed as a separate revenue category, indicating that increased design adoption has begun shifting toward commercial production. At this stage, however, its contribution to revenue remains small compared with N3 and N5.
A concrete example confirmable on the customer side is AMD's 6th-generation EPYC "Venice." On May 21, 2026, AMD announced it had begun production ramp-up of Venice in Taiwan, positioning it as the first HPC product to enter the production stage on TSMC's 2nm process. AMD has also announced a successor 2nm product, "Verano." The move of a large-area server CPU chiplet into mass production shows that N2's revenue composition is not determined solely by the timing of mobile product launches. That said, AMD has not disclosed a general shipment start date or customer deployment status, so "production ramp-up" cannot be read as equivalent to "sales launch."
On the mobile side, MediaTek announced in September 2025 the tape-out of a flagship SoC using N2P, with mass production and product availability expected in the second half of 2026. The targets it presented versus N3E were up to 18% performance improvement at the same power, roughly 36% power reduction at the same speed, and 1.2x logic density. These are figures for the enhanced N2P, not baseline N2, and they are not guarantees of actual product speed, battery life, or die size. Even so, the fact that server CPUs and mobile SoCs ramp up at different times suggests that a high tape-out count may convert into revenue gradually over several quarters.
Looking at N3's early trajectory shows there is a time lag before advanced nodes translate into revenue. N3 began mass production in Q4 2022, and its wafer revenue share rose to 6% in Q3 2023 and 15% in Q4 2023. This is not a directly comparable controlled experiment against N2's 3%, since customer product launch timing and die size differ, as do pricing and utilization rates. There is no relationship whereby fourfold tape-outs produce fourfold revenue in the same quarter; monetization will proceed in stages as future products launch.
87 Days of Inventory and a 2–3 Point Margin Burden
Even with strong design adoption, factory-side costs run ahead during the ramp-up phase of an advanced node. TSMC is expanding N2 production across multiple phases in both Hsinchu and Kaohsiung. In Q2 2026, days of inventory rose by 7 days from 80 days in the previous quarter to 87 days, with the company citing N2's production expansion as the main reason. This is the phase in which work-in-process wafers increase and work-in-progress inventory and raw materials build up ahead of revenue recognition.
The impact on profitability has also been quantified. TSMC expects N2's ramp-up to reduce full-year 2026 gross margin by 2–3 percentage points. New processes involve overlapping costs from equipment depreciation, initial utilization rates, and yield-improvement expenses. Even an advanced node capable of commanding a high price does not necessarily reach the company-wide average profit margin immediately after entering mass production.
N3, having gone through this earlier, offers a reference for the timeline involved. N3 began mass production in Q4 2022, but TSMC expects it to reach and exceed the company-wide average gross margin only in the second half of 2026. For N2 as well, converting fourfold tape-outs into production volume will require factory expansion, per-customer product qualification, and yield improvement. While a thick pipeline of projects supports long-term facility utilization, a concentration of ramp-ups also swells inventory and costs.
The next thing to watch is whether the rise in wafer revenue share and improvement in profitability proceed in tandem. Even if N2's revenue share alone rises, if the margin pressure persists, the costs of the mass-production ramp-up will remain. Because days of inventory is a company-wide metric, moved also by demand and materials unrelated to N2, a decline in that figure alone cannot be taken as proof that N2's work-in-process has converted into revenue. In addition to quarterly N2 wafer revenue share and gross margin, days of inventory must also be tracked. The factors behind changes in each metric, as explained by the company, are likewise indispensable. All of these lag behind tape-out counts, but they serve as material for verifying progress as a manufacturing business.
From N2P to N2U: Not Ending 2nm with a Single Generation
TSMC is not rolling out 2nm as a single-specification process. N2P, with improved performance and power, is scheduled for mass production in the second half of 2026, and the Japan symposium indicated roughly a 5% performance improvement over N2. N2X, aimed at high-performance applications, follows in 2027, targeting roughly a 10% performance improvement over N2. The structure is to establish a mass-production foundation with baseline N2 and then branch into derivative versions according to the performance tier and launch timing customers require.
"N2U" is planned for 2028. According to TSMC's official announcement, it targets a 3–4% speed improvement over N2P, or an 8–10% power reduction, along with 1.02–1.03x logic density. That same year, AEC-Q100 certification for the automotive-oriented "N2A" is also planned, and an automotive Auto-Use kit is already available in N2P's design kit. This is a roadmap that extends the GAA generation—which began with smartphones and HPC—into long-lifecycle product categories including automotive.
The abundance of derivative versions also means that N2's tape-outs will not necessarily continue concentrating on the same specification going forward. Each process within the N2 family has different launch timing and targets, and A16, which moves power routing to the wafer backside, represents yet another option. The current "fourfold" statement should not be treated as a combined figure encompassing orders or production capacity across all these generations.
The next indicators for assessing N2's ramp-up are the quarterly wafer revenue share, the start of N2P mass production, days of inventory, and the impact on gross margin. The fourfold tape-out figure showed that a large number of designs have gathered around TSMC's transition to GAA. The 3% wafer revenue share and the 2–3 percentage point margin burden show that the process of converting this into factory profitability has only just begun. It will be possible to judge that design momentum has translated into mass-production scale only once, amid the continued rollout of derivative processes, both the revenue share and profitability have improved.