On June 17, 2026, research teams from South Korea and Japan presented two designs that orient HBM's DRAM dies 90 degrees from the conventional stacking direction. "V-Die" and "MOSAIC" appeared side by side in the same DRAM session at the IEEE/JSAP Symposium on VLSI Technology and Circuits 2026. Both approaches stand the DRAM dies upright, orthogonal to the GPU. The goal is to change how capacity, signaling, and heat are scaled, moving away from today's HBM approach of simply stacking dies ever higher.
However, the two projects are not at the same stage. V-Die is a design proposal that compares bandwidth, capacity scalability, and thermal characteristics against current HBM, and the published abstract does not disclose detailed prototype results. MOSAIC, by contrast, has built a prototype of contactless die-to-die communication and demonstrated up to 4Gbps per channel. Anyone considering what comes after HBM needs to read these two proposals with this difference in mind.
The Next Wall After HBM4's 2048-Pin Expansion
HBM stacks DRAM dies and connects them vertically using through-silicon vias (TSVs). Placed close to the GPU, it moves large volumes of data over an extremely wide bus even at low clock speeds. This structure has eased the bandwidth shortage faced by AI accelerators, but as capacity increases and the stack grows taller, the path for heat to escape from the center of the stack grows longer.
HBM4 tackled this head-on by widening the bus. According to Micron's current product information, the interface has 2048 pins—double the previous generation—with signal speeds exceeding 11.0Gbps and per-stack bandwidth surpassing 2.8TB/s. Bandwidth has more than doubled compared to the prior generation. Micron also states that, compared with the same 12-layer HBM3E configuration, power efficiency per bit transferred has improved by more than 20%. SK hynix likewise cites 2048 I/O pins and speeds exceeding 10Gbps.
As these numbers grow larger, so does the burden on packaging. Engineers must route the wide I/O to the GPU, carry heat generated inside the stack out to the exterior, and keep all of this within acceptable yield and cost limits. Rather than starting by changing memory cells or signal speeds, V-Die and MOSAIC address this problem by changing the orientation of the dies themselves.
V-Die Runs Cooling Channels Between the Dies
V-Die is a "3.5D" configuration that stands DRAM dies—fabricated using standard processes—upright on a substrate. According to the VLSI Symposium abstract, this expands the exposed surface area of each die and allows liquid to flow directly between adjacent dies. Unlike a stacked structure cooled from the top, this approach can use the side faces near the heat source itself as a cooling pathway. Because capacity can also be increased laterally rather than by height, the concept allows the number of dies to grow while preserving cooling surface area.
A KAIST laboratory in South Korea is advancing V-Die as a joint research effort with Hanbat National University and the Ulsan National Institute of Science and Technology (UNIST). The lab was selected for Samsung's Future Technology Development Program in October 2025. The program runs from December 2025 through December 2030, with plans to jointly optimize the connection and cooling of vertically standing chips for AI accelerators.
This extended development timeline also reflects where V-Die currently stands. The published conference abstract describes a comparative evaluation of bandwidth, capacity scalability, and thermal behavior against state-of-the-art HBM, but does not yet show a prototype at product dimensions, long-term reliability data including the cooling liquid, or manufacturing yield. Routing liquid between dies requires incorporating channel pressure loss, sealing, corrosion, leakage, and maintenance into the package design. The next stage will be whether the thermal-simulation advantages can be translated into a cooling system that can actually be mass-produced.
MOSAIC Sidesteps Assembly Tolerances with Magnetic Fields
The University of Tokyo's MOSAIC (Massive Orthogonal Stacking Assembly of IC) offers a different answer to the question of how to connect upright dies. Small coils are formed on both the die and the GPU side, and data is transferred via inductive coupling. Because signals can be delivered without mechanically stacking metal contacts one by one, this approach more easily absorbs variation in die thickness and assembly position.
According to the official VLSI Symposium abstract, the prototype contactless interface operated at up to 4Gbps per channel. The design integrates DRAM three-dimensionally onto the GPU without using TSVs, and for the configuration studied, it is said to enable memory capacity twice that of HBM4-class devices. Note that 4Gbps is a per-channel figure, not the bandwidth of the entire package. A comprehensive comparison against HBM4, with its 2048 I/O pins, will only be possible once the channel count, interference during simultaneous operation, and energy consumption per bit are all established.
Inductive coupling itself is not a technology that appeared out of nowhere. In 2010, the University of Tokyo's Kuroda Laboratory demonstrated 1024 channels between a 65nm GPU and 0.1µm DRAM, achieving a combined 8Tbps at 1pJ/bit. What is new about MOSAIC is that it connects this long-accumulated body of work on contactless communication to the specific problems of assembly tolerance and heat dissipation created by orthogonally stacked DRAM dies.
At the same time, even if data transfer is made contactless, power still needs to be delivered somehow. Power-delivery terminals must be fit into the same three-dimensional structure while keeping coil area and coupling between adjacent channels under control. Managing heat generation and finding ways to detect defective spots during mass production remain essential challenges. Whether a faulty die can be replaced is also still an open question. Turning the design advantage of doubled capacity into real product value will require refining the communication circuitry and the assembly process together, as a single integrated effort.
Manufacturing Reproducibility, Not Speed, Will Decide Mass Production
Both proposals decouple HBM's heat problem from the trajectory of "stack ever-thinner dies ever higher." V-Die introduces cooling liquid between the dies, while MOSAIC uses contactless communication to relax the need for precise contact alignment. Because both approaches use lateral area, they create new trade-offs with the package area around the GPU, cooling piping, and signal routing. Rather than eliminating the constraints of the vertical direction, these are technologies that shift the design burden to a different direction.
What's needed to judge commercial viability is clear. V-Die needs electrical characterization using actual dies and longevity testing of the cooling system. MOSAIC needs to demonstrate total bandwidth, power consumption, and error rate when the single-channel 4Gbps result is scaled up to many channels. What both share in common is the requirement to maintain assembly precision and yield even as the number of stacked layers increases, and to be inspectable using existing GPU packaging processes.
HBM4 has already advanced to product bandwidths exceeding 2.8TB/s. For these research proposals to become viable successors, showing a structure that runs cooler is not enough. They must measure bandwidth and capacity using the same prototype package, and disclose temperature and yield data as well. Can a laterally expanded design demonstrate that it lowers power consumption and cost for the system as a whole? That full package of evidence is what we want to see confirmed at the next conference presentation.