On August 20, 2026, Waymo publicly detailed the onboard computer and custom 5nm-process ASIC of its sixth-generation Waymo Driver for the first time. The eye-catching figure is "over 1,000 TOPS," but this is not the compute performance of a single chip. It is the combined rated performance of multiple ASICs that work together to fuse raw data from cameras, LiDAR, and radar, and to run neural networks.
What this disclosure reveals is that Waymo does not consolidate its self-driving compute onto a single high-performance SoC. Instead, it places dedicated processing directly behind the sensors and combines it with CPUs, GPUs, and other accelerators. Ojai, the new vehicle carrying the sixth-generation Driver, welcomed its first passengers on June 10. Waymo initially offered the service in Phoenix, Los Angeles, and San Francisco. This means the computing design disclosed here is not a concept for research vehicles, but the architecture of a generation already in passenger operation.
According to Waymo, the requirements for its onboard computer were set based on more than 200 million miles of fully autonomous driving experience. The company says it has increased raw compute power twentyfold over eight years. However, measuring what's new here by TOPS alone misses how the work is divided between sensors and control. What determines the role of this ASIC is which data gets processed first by dedicated circuits, and at what point the work is handed off to general-purpose compute.
What the 1,000+ TOPS Actually Handles: Pre-Processing, Sensor Fusion, and Model Execution
The latest system processes data from 13 high-resolution cameras simultaneously, in real time. Overall, the sixth-generation Driver combines 13 cameras with four LiDAR units and six radar units. In its February announcement, Waymo explained that next-generation 17-megapixel imagers allow full coverage of the vehicle's surroundings with fewer cameras than would be needed with 5-megapixel or 8-megapixel units. August's disclosure supplied the computing-side answer to how these higher-resolution images are handled inside the vehicle.
The ASIC specializes in pre-processing sensor data, fusing it, and executing machine learning models. In low-light conditions, a dedicated accelerator handles temporal denoising, which uses information captured at preceding and following moments. Waymo says it runs a range of different models, from sparse convolutions to dense transformers, and that it co-designed the sensors, algorithms, and ASIC together.
The pre-processing referred to here is the work of preparing images into a state usable for driving decisions before handing them over wholesale to the core AI. If a fixed sensor pipeline is handled in small batches, it becomes easier to offload tasks—including data movement and quantization—onto dedicated circuits. This is an implication that can be drawn from Waymo's explanation of co-design, but the company has not disclosed power-reduction figures or the latency of individual steps.
Under the condition of handling 13 cameras simultaneously, simply processing each frame faster is not enough. Noise reduction that references preceding and following moments in low light, the process of combining information from different sensors, and the conversion into representations used by downstream recognition models form a continuous chain from input to control. When Waymo says it has shortened "pixels-to-actuation" latency, this includes that entire chain of handoffs. However, the company has not disclosed how many milliseconds were cut at which stage.
All driving decisions are completed entirely on board the vehicle, and Waymo says processing happens on the order of single-digit milliseconds. The company also says it has reduced the latency of the full stack—"pixels-to-actuation," meaning the path from inputs like cameras to actually operating the vehicle. However, neither the before-and-after latency nor the absolute figures have been shown. Nor can "over 1,000 TOPS" simply be read as equivalent to low latency.
Even With Its Own ASIC, Waymo Still Relies on CPUs and GPUs
Waymo's onboard computer is not composed of dedicated ASICs alone. It's a heterogeneous system that uses CPUs, GPUs, and accelerators selectively, and also handles non-machine-learning tasks such as orchestration, data movement, and logging. Within this system, the ASIC is positioned as the component responsible for receiving sensor input and handling fusion and model execution.
This division of roles is also why adopting an in-house chip cannot be characterized as "a complete shift away from external vendors." Waymo names AMD, Micron, and NVIDIA as collaboration partners, and it also works with Samsung, TSMC, and others. However, Waymo has not disclosed the foundry for the 5nm ASIC, the specific process variant used, or how the work was divided among these partners. Claims that Waymo adopted TSMC's N5A process, or that it replaced NVIDIA products, cannot be drawn from the information disclosed so far.
Back in February, Waymo indicated a policy of shifting some sensor and processing complexity onto custom silicon for the sixth-generation Driver. This latest disclosure clarifies that the custom silicon is not a single brain handling all onboard compute, but rather sits among multiple compute resources. Retaining general-purpose compute is also a way to avoid cramming onboard processing—which includes control and logging beyond just models—into the same circuitry.
Splitting compute by role also leaves room for models to change. The sparse convolutions and dense transformers that Waymo mentioned differ both in how their computational load is distributed and in how they handle required data. Rather than fixing all driving software onto the front-end ASIC, Waymo assigns it input processing that is easy to specialize, and combines that with the remaining compute resources, including CPUs and GPUs. Exactly which models are assigned to which part of this division has not yet been made public.
Two Independent Engines Sustain Operation Through Failures
Unlike a data center, a vehicle cannot wait for a failed component to be shut down and replaced. Waymo's onboard computer is designed as though it were two independent engines, running fully parallel workloads under normal conditions. If one fails, the other takes over. This is not parallelization aimed at boosting compute performance—it's a redundancy design meant to keep the vehicle driving.
However, this is not a disclosure stating that there are two ASICs. The number "two" refers to independent engines within the computing system, and how many chips of what type each engine contains has not been revealed. The ASIC's official name, die size, and transistor count remain undisclosed, and its memory capacity, bandwidth, and power consumption are also unknown. Circuit redundancy and component count cannot be treated as the same thing.
Waymo says it connects the computer directly to the vehicle's liquid-cooling system, designing it to maintain performance under vibration, shock, and extreme temperatures. Battery efficiency, trunk space, and quiet operation were also cited as requirements for a passenger vehicle. None of these come with figures showing the degree of improvement, but achieving both fully on-board low latency and redundant computing at once requires cooling and packaging to be addressed alongside raw chip performance.
If two systems run in parallel from the start under normal conditions, unlike a standby system that only activates in emergencies, both must be kept in a state usable for driving. Measures for cooling, vibration, and temperature appear in the same announcement precisely because this computer is meant for continuous operation within a vehicle's limited space, not for producing benchmark performance figures. Waymo listed conditions relevant to passenger vehicles, but it has not provided numbers showing the relationship between each condition and the ASIC's power draw or heat generation.
Why the Numbers Can't Simply Be Lined Up Against NVIDIA Thor
NVIDIA's DRIVE AGX Thor claims up to 1,000 INT8 TOPS and 2,000 FP4 TOPS on a single SoC. Its published specifications also include 64GB of LPDDR5X, up to 273GB/s of memory bandwidth, and camera input via 16 GMSL2 lanes and 2 GMSL3 lanes. At first glance, this looks close to Waymo's figure of "over 1,000 TOPS."
However, Waymo's figure represents the combined rated performance of multiple ASICs for pre-processing and machine learning models, without specifying either the numerical precision used or how many ASICs are involved. Memory, power, and real-world performance also remain unknown. Thor's figure, by contrast, is the rated value for a single SoC. The role each figure represents and the level of detail disclosed simply differ. Placing the two numbers side by side cannot support a conclusion about which is superior.
Notably, Thor presents separate performance figures for INT8 and FP4, whereas Waymo simply states "over 1,000 TOPS" for "these ASICs" collectively. When precision differs, the same unit of TOPS carries different underlying assumptions. To meaningfully compare a group of ASICs dedicated to sensor fusion against a single SoC whose camera I/O and memory specifications are fully disclosed, one would need to align at minimum the precision used for each process, the number of ASICs, the onboard memory, and power consumption.
Hot Chips 2026 will be held from August 23 to 25, and Waymo has scheduled a keynote by Daniel Rosenband at 2:15 PM Pacific Daylight Time on August 24, followed by a talk on the sensor fusion processor at 3:15 PM. If the company discloses the number of chips, the numerical precision used, memory configuration and power consumption, and the effective latency from input to actuation, it will finally become possible to verify—on a common basis—exactly what portion of vehicle processing "over 1,000 TOPS" actually covers.