On August 18, 2026, technology observer tphuang shared a slide bearing the XUANTIE label. It claimed that with a 64-core XuanTie C950 target configuration, Qwen3.8-27B achieved decode performance of 30+ tokens/s and a time-to-first-token (TTFT) of 1.9 seconds. This is not an independently reproduced result.
Back in March, an explanation of compatibility was presented, stating that the chip "natively supports models at the scale of Qwen3 and DeepSeek V3." This time, current model names along with latency and generation speed figures have been added. In C950's AI inference, competitiveness hinges not just on CPU peak performance, but on how model operators are implemented and how intermediate data in memory is reduced.
The measurement conditions leave many gaps. To understand how far these numbers can speak to actual product performance or comparisons against GPUs, we need to separate the boundaries between the library, the model, the processor IP, and the actual system.
30 Tokens/s on a 64-Core Configuration: The Two Figures in the Materials
According to the slide, Qwen3.8-27B ran on a 64-core C950 target configuration achieving decode speeds of 30+ tokens/s with a TTFT of 1.9 seconds. Decode refers to the metric indicating how many tokens per second can be output once generation has begun. TTFT represents the time from receiving input to returning the first output. In conversational inference, the former shapes the flow of responses, while the latter determines the initial waiting time.
The same slide also lists a figure for Qwen3.8-2.4T-A95B: decode at 7.2 tokens/s with a TTFT of 8.5 seconds. Since the two models differ in scale, and precision, input, and memory conditions remain unknown, the difference in figures cannot be explained by scale alone. What can be confirmed is only that the XUANTIE materials listed both the 27B and 2.4T-A95B models as targets for C950 optimization.
The slide merely refers to this as a "C950 target configuration." It does not disclose the board, memory type/capacity/bandwidth, numerical precision or quantization, batch size, prompt and context length, power consumption, or sampling settings. Consequently, the figures of 30 tokens/s and 1.9 seconds cannot be directly placed alongside published figures for other CPUs, Macs, or GPUs.
What Makes It Fast: SHL and Vector/Matrix
Behind these numbers lies multi-layered optimization via XuanTie's Heterogeneous Neural Network Library, SHL. According to the materials, SHL selects matrix kernels for MatMul and Linear operations based on precision and computational shape, while using dedicated implementations for Softmax and RMSNorm. In large language model inference, such operator-by-operator differences accumulate into execution time.
The slide further states that reordering of processing sequences, preprocessing, buffer reuse, and operator fusion reduce format conversions, memory allocation, and reading/writing of intermediate data. Even if the computational units are made faster, if data movement remains, inference latency won't shrink. What these materials primarily demonstrate is not the number of cores in C950 itself, but the software that connects computation and memory processing to model execution.
C950 is publicly presented as a server-class RISC-V processor IP for cloud and data centers, AI agent servers, and high-performance robotics. The official page cites 8-instruction decode, out-of-order execution, and vector computation. It also features Matrix AI acceleration, RVA23 Profile, and CoVE. Alibaba's March announcement similarly described a RISC-V CPU combined with Vector and Matrix acceleration engines, natively supporting models at the scale of Qwen3 and DeepSeek V3.
SHL's public repository lists CPU assembly optimization, support for 8-bit, 16-bit, and f16 formats, symmetric and asymmetric quantization, heterogeneous scheduling, and optimized binaries. However, since C950 also features Matrix AI acceleration, it cannot be said that this inference pathway was completed on the CPU alone. Any connected accelerators or offload pathways remain undisclosed as well.
The Weight of Qwen3.8-27B and Gaps in Measurement
According to Qwen's official model card, Qwen3.8-27B is a dense vision-language causal model with 27 billion parameters, with the language model layer consisting of 64 layers. Its native context length is 262,144 tokens, extendable up to 1,000,000 tokens. Since input length strongly affects TTFT, understanding the 1.9-second figure requires knowing what prompt length was used.
The official files were uploaded between August 12 and 14, meaning the C950 materials from the 18th appeared just days after the open model's release. Demonstrating library-side support in step with the model's debut is more concrete than March's broad compatibility claims. Nevertheless, being able to run a freshly released model is distinct from being able to run it stably across a wide range of usage conditions.
Without knowing the precision, quantization, and batch settings, it remains unclear to what extent the measurement prioritized speed versus efficiency. Memory bandwidth also remains undisclosed. Without power figures, performance-per-watt cannot be evaluated either. It is reasonable to treat today's figures as vendor-side metrics representing what the combination of C950 and SHL achieved, but they are not yet sufficient grounds for constructing an efficiency comparison table.
Not Conflating IP, Target Configuration, and Mass Production
C950 is processor IP that customers configure and integrate themselves. Therefore, benchmarks obtained from a 64-core target configuration do not confirm mass-produced chip shipments, system delivery, pricing, yield, or data center deployment. Even after connecting optimizations from the model to the library to processor features, mass-production design and verification remain necessary before delivery as a commercial system.
Regarding manufacturing, Nikkei Asia reported that C950 was verified on a 5nm process, with sources indicating the possibility of TSMC production. Since Alibaba has not disclosed its manufacturing partner, TSMC production is not a confirmed fact. Nor can it be definitively stated that C950 will be mass-produced at 5nm.
Wccftech reported on the August 18 materials as "day-zero support." To substantiate the speed of this implementation, reproducible measurements under identical conditions are needed, along with disclosure of precision and context length. Memory configuration and power consumption would also be required. Once it becomes clear when and in what configuration products featuring C950 will emerge, we will be able to judge whether these optimizations translate into real-world deployment.