Chinese chipmaker YMTC (Yangtze Memory Technologies) is reportedly developing a new low-power DRAM that uses a vertical channel transistor (VCT). According to research published by Counterpoint Research on October 13, 2026, the DRAM adopts a 4F² cell structure and targets a data transfer rate of 9,600 MT/s. If the performance target is met, the company plans to mass-produce it at its Fab 3.
YMTC is already testing 7,500 MT/s LPDDR5 at Fab 2, but that product differs in both design and development stage from the 9,600 MT/s device now being reported. The information also comes from a research firm's report; YMTC itself has not announced the start of mass production. What matters is not only the speed target, but how the company will use the transistor structure and wafer-bonding technology, and how it will carry them through to actual mass production.
Fab 2 testing and Fab 3 mass-production plans are separate efforts
LPDDR is a type of low-power DRAM used in devices such as smartphones. Data transfer rates are expressed in MT/s (megatransfers per second). Counterpoint Research describes YMTC's product as "LPDDR5"; no formal "LPDDR5X" specification or product name has been confirmed.
According to Counterpoint Research's report, YMTC has been conducting R&D and testing of a second-generation 16Gb LPDDR5 at Fab 2 since October 2025. Its data transfer rate is 7,500 MT/s, and wafer input is reported at about 5,000 wafers per month. However, the company is reported to have no plans to mass-produce this product.
The 9,600 MT/s DRAM now under development, by contrast, uses a 4F² cell structure built on vertical channel transistors. Mass production at Fab 3 is planned, conditional on meeting the performance target. In other words, YMTC is not simply speeding up the Fab 2 test product for mass production; it is developing a product with a different design as the next mass-production candidate.
| Item | Data transfer rate | Capacity | Development/production site | Current stage |
|---|---|---|---|---|
| 2nd-gen LPDDR5 test product | 7,500 MT/s | 16Gb | Fab 2 | R&D and testing. No mass-production plan |
| VCT / 4F² development product | 9,600 MT/s (target) | Unconfirmed | Fab 3 (planned mass production) | Mass-production plan conditional on meeting performance target |
One caveat concerns the figure of roughly 5,000 wafers per month at Fab 2. This is the scale of wafers input for R&D and testing; it does not mean the same number of sellable, good wafers are being produced. The 16Gb capacity also refers to the product being tested at Fab 2, and the Fab 3 development product will not necessarily have the same capacity.
At this point, there is no information confirming that the 9,600 MT/s target has been achieved in measurements, nor when mass production at Fab 3 will begin. What the report reveals is not that YMTC has begun commercial supply, but the structure it plans to use in its next mass-production candidate, its performance target, and the conditions for moving to mass production.
How do VCT, Xtacking and 3D DRAM differ?
To understand YMTC's new DRAM, it is important to distinguish between the vertical channel transistor (VCT), the wafer-bonding technology "Xtacking," and 3D DRAM. All three relate to using semiconductor structures in three dimensions, but each changes a different part of the chip.
VCT is a structure in which the channel through which current flows inside the transistor is formed vertically. 4F² and 6F², meanwhile, are metrics for the area a memory cell occupies on a plane, where F is the minimum feature size in semiconductor manufacturing. The 4F² and 6F² figures express area as a multiple of F squared; they do not indicate the number of stacked memory cell layers. This distinction is also explained in a University of California, Berkeley doctoral dissertation (Figure 1.4).
Xtacking, by contrast, is a technology for bonding separately manufactured wafers, while 3D DRAM refers to a structure in which memory cells themselves are stacked in multiple layers. Placing transistors vertically, bonding wafers together, and stacking memory cells are therefore distinct technical efforts.
| Technology | What it changes | Position of the technology |
|---|---|---|
| VCT | Forms the transistor's current path vertically | Technology reported to be used by YMTC in its 4F² DRAM |
| Xtacking | Manufactures the cell side and peripheral circuit side on separate wafers, then bonds them | Wafer-bonding technology YMTC has used in NAND |
| 3D DRAM | Stacks DRAM memory cells in multiple layers | Technology for higher DRAM density in the future |
This table organizes which part of the semiconductor each technology modifies; it is not a performance comparison under identical conditions. Making transistors vertical with VCT does not by itself produce a 3D DRAM with multilayer memory cells.
So how could Xtacking, which YMTC developed through NAND flash memory, help in DRAM? According to YMTC's official explanation announced on August 6, 2018, Xtacking manufactures the memory cells and the peripheral circuits that control their operation and data input/output on separate wafers. The two wafers are then electrically connected through metal interconnects. Manufacturing the memory cells and peripheral circuits separately allows each to use a process suited to it.
The key point is that memory cells and peripheral circuits can be made separately and bonded at the end. However, the 2018 explanation concerned NAND flash memory; it is not evidence that YMTC has implemented the same technology in DRAM or achieved high yields. Technical experience in NAND must be distinguished from a mass-production track record in DRAM.
Counterpoint Research reports that YMTC envisions extending Xtacking to DRAM as well. The firm's Neil Shah analyzes that, as the shift to 3D DRAM progresses in the future, manufacturers with wafer-bonding experience such as YMTC could gain a competitive advantage. This is an outlook on future technology competition, however, and does not mean YMTC has already reached the stage of being able to mass-produce 3D DRAM.
The 4F² VCT structure is also not the only technical option for increasing DRAM density. Tokyo Electron's (TEL) Investors Guide dated September 15, 2026 (page 63) presents two paths beyond the conventional 6F² structure, "4F² VCT" and "6F² + peripheral circuit bonding," with 3D DRAM positioned beyond them. This is a general technology roadmap by TEL as of August 6, 2026, and does not show the manufacturing process of any specific maker such as YMTC.
The roadmap also shows that changing the cell structure and bonding peripheral circuits could develop as separate technologies. It is not possible to determine from TEL's document which process YMTC will adopt at Fab 3, but the value of wafer-bonding technology need not be judged solely by the move to 4F². How far the technology cultivated through Xtacking can be applied to DRAM manufacturing will be a key question going forward.
In the DRAM market, mass-production track record matters as much as speed
In evaluating YMTC's development plan, it is also necessary to consider how it differs from competitors already in mass production. China's DRAM maker CXMT (ChangXin Memory Technologies) announced on September 20, 2026 mass production of its fifth-generation manufacturing platform "G5" and two LPDDR5X products using it. These have a capacity of 24Gb per die and target smartphones and portable consumer devices.
YMTC's 9,600 MT/s product is a conditional mass-production plan reported by Counterpoint Research. CXMT's LPDDR5X, on the other hand, is a product whose mass production the manufacturer itself has announced. Because the source of information and the stage of productization differ, it is not possible to judge which is technologically ahead by simply comparing data transfer rates.
The figures CXMT disclosed also require careful reading of the comparison conditions. The company explains that the 24Gb capacity is a 50% increase over the equivalent previous-generation product. Meanwhile, it says G5 increased the total number of dies per wafer (DPW) by more than 50% versus the previous generation, but that comparison is normalized to an 8Gb capacity. In other words, a 50% increase in capacity per die and a more-than-50% increase in dies per wafer at equal capacity are different metrics.
Conflating the two and interpreting it as "50% more finished 24Gb products can be made from the same wafer" is not accurate. DPW is a metric of the total number of dies formed on a wafer, and does not directly indicate the number of shippable good dies or manufacturing yield. In the DRAM mass-production race, differences in such metrics greatly affect assessments of production capacity and manufacturing cost.
Similarly, for the 4F² structure YMTC aims to adopt, it is impossible to calculate the overall chip area, the number of good dies per wafer, or the rate of manufacturing cost improvement from the cell-area notation alone. Even if the 9,600 MT/s speed target is achieved, the performance obtained in actual smartphones and the product's competitiveness will also depend on capacity, power consumption, manufacturing cost, quality, and other conditions.
In evaluating YMTC's DRAM business going forward, the first thing that matters is whether it can achieve the 9,600 MT/s performance target. Beyond that, the question is whether it can pass quality qualification and actually move to mass production at Fab 3. The change in cell structure through VCT and the wafer-bonding technology accumulated in NAND may lead to future competitiveness. But that advantage can be judged only after it is confirmed that the new design can be manufactured with stable quality and yield and supplied continuously to the market.