At "Advancing AI 2026" on July 23, 2026, AMD unveiled detailed specifications for its next-generation AI accelerator, the "Instinct MI455X," along with "Helios," a rack design that houses 72 of these GPUs. The MI455X features 432GB of HBM4 per GPU, and its theoretical peak performance for 4-bit operations reaches 40PFLOPS. The "rack delivering up to three exaFLOPS" that AMD previewed at CES 2026 has now advanced into a concrete design that connects GPUs and CPUs over a network, and incorporates power delivery and liquid cooling.
What AMD is aiming for is a shift from competition over the performance of individual GPU cards to competition over the ability to run models across an entire rack. Both Helios and NVIDIA's Vera Rubin NVL72 are 72-GPU rack configurations, but Helios foregrounds industry standards such as Open Rack Wide, UALink, and Ethernet. That said, theoretical numbers alone do not determine actual generation speed or operating costs. Whether the MI455X can actually outperform in real products will be decided by measurements going forward.
432GB of HBM4 and 40PFLOPS
The MI455X adopts the 5th-generation CDNA architecture and is equipped with 256 WGPs (Work Group Processors). The theoretical peak figures AMD has published are 40PFLOPS for OCP MXFP4, 20PFLOPS for 8-bit operations, and 5PFLOPS for FP16/BF16 matrix operations. Its HBM4 comes in 12 stacks totaling 432GB, with bandwidth reaching up to 23.3TB/s.
The previous generation MI355X had 288GB of HBM3E and 8TB/s of bandwidth, with MXFP4 at 10.1PFLOPS and MXFP8 at 5PFLOPS. With the MI455X, memory capacity has increased by 50%, and bandwidth has grown to approximately 2.9 times that of its predecessor. The "up to 4x" improvement in low-precision computing performance that AMD touts also corresponds to a comparison between 40PFLOPS and 10.1PFLOPS. However, these are theoretical peak figures calculated by AMD, and actual results will vary depending on data types and system configuration.
The increase in HBM capacity allows more model weights, KV caches, and intermediate training data to be kept in local memory. Reducing the number of times data must be offloaded outside the GPU is advantageous for long-context or high-concurrency inference workloads. On the other hand, fully utilizing this capacity requires software that efficiently controls data placement and communication. AMD states that ROCm will support PyTorch, TensorFlow, and JAX from day one. vLLM and Triton will also be supported for inference infrastructure.
Bundling 72 Units into a Single Computer
Helios repeatedly arranges compute trays, each loaded with four MI455X units, to fit 72 GPUs into a single rack. The host uses the 6th-generation EPYC "Venice," combined with Pensando "Vulcano" AI NICs for inter-rack communication and "Salina" DPUs for front-end networking and storage processing. The rack's overall stated figures are 2.9 exaFLOPS for OCP MXFP4, 1.4 exaFLOPS for OCP MXFP8, 31TB of HBM4, and a theoretical memory bandwidth of 1.67PB/s.
For scale-up connections between GPUs, AMD adopted UALink over Ethernet, using Ethernet as the physical layer. The stated bandwidth reaches 260TB/s across the entire rack. Furthermore, racks are connected to each other via Ethernet designed with UEC (Ultra Ethernet Consortium) compliance in mind, claiming a scale-out bandwidth of 43TB/s. By adopting OCP, UALink, and UEC, AMD has chosen a design that multiple equipment manufacturers can implement.
The chassis is based on the double-width Open Rack Wide that Meta submitted to the Open Compute Project. In line with the increased density, a central power shelf and vertical busbars are placed, and cooling fluid is distributed from liquid cooling manifolds to the compute trays and switches. The design also incorporates features that reduce rewiring during tray replacement. Beyond computing performance, the rack design also addresses how much downtime maintenance requires.
Reading the Comparison with Rubin Through Memory
NVIDIA's Rubin GPU features 288GB of HBM4 and 22TB/s of memory bandwidth per unit. This means the MI455X exceeds it by 50% in capacity and about 6% in bandwidth. For per-GPU scale-up bandwidth, both the MI455X's UALink over Ethernet and Rubin's NVLink 6 claim 3.6TB/s. AMD has room to spare in terms of how much of a large model can fit within the GPU, while the stated bandwidth for inter-GPU communication is on par between the two.
Computing performance is harder to interpret numerically. AMD states the MI455X's OCP MXFP4 at 40PFLOPS, while NVIDIA states Rubin's NVFP4 inference performance at 50PFLOPS, but the numerical formats and calculation conditions differ. The comparison AMD presents, claiming to be "15% higher than the competitor," is also AMD's own theoretical calculation using NVIDIA's preliminary specifications. In actual models, throughput is determined by quantization methods that preserve accuracy, how communication overlaps with computation, and the optimization of ROCm versus CUDA.
The unit of competition has also shifted from individual GPUs to entire racks. The Vera Rubin NVL72 connects 72 Rubin GPUs and 36 Vera CPUs via NVLink, while Helios combines EPYC with Ethernet-based open standards. Both are integrated designs that include power and liquid cooling. What users choose is not the peak value of the accelerator, but an infrastructure that encompasses the effort of swapping models, cost per token, and operations during failures.
Real-World Performance Put to the Test After Shipping
Helios is not a rack that AMD sells as a finished product. It is a reference design for OEMs and ODMs to build systems under their own brands. AMD has shared the design with partners, and expects mass deployment in the second half of 2026. Microsoft has also adopted Helios for Azure's large-scale inference infrastructure, and AMD states that shipments to customers, including Microsoft, will begin in the latter half of the same year.
According to Phoronix, which covered Advancing AI 2026 on-site, Helios has entered full production, with shipments beginning later this quarter and expanding from Q4 2026 through the first half of 2027. This is a more specific timeline than the broad "second half of 2026" officially announced, though the general availability dates for individual OEM products or cloud services have not yet been finalized.
Significant gaps remain. AMD has not disclosed the power consumption or pricing of the MI455X, and there are no third-party benchmarks yet using major models. A figure like 2.9 exaFLOPS alone cannot tell us the power capacity, cooling infrastructure, or cost per token that a data center would require.
Once Helios-equipped systems begin operating in the latter half of 2026, the first thing that can be confirmed is how much the 432GB of HBM4 reduces the need to offload data outside the GPU during long-context inference or with large-scale models. Following that, measuring how well ROCm can overlap communication and computation across 72 GPUs will reveal whether the theoretical peak advantage of 4x for OCP MXFP4 over the MI355X actually manifests in real-world operation.