On August 18, 2026, Cerebras Systems unveiled its rack-scale AI system, the "CS-4." Each rack houses three Wafer Scale Engine 3 Turbo (WSE-3T) units, and each WSE-3T claims 250 PFLOPS of sparse FP16 peak compute performance per wafer. That's double the WSE-3's 125 PFLOPS, and the company also reports achieving over 4,400 tokens per second per user on GPT-OSS-120B.
What's notable is that the WSE-3T hasn't moved to a new manufacturing process. TSMC's 5nm node, 4 trillion transistors, 900,000 cores, and 44GB of on-chip SRAM all remain unchanged. Instead, Cerebras moved power delivery and cooling much closer to the wafer and rebuilt the I/O and rack architecture around it. CS-4's performance ultimately comes down to how far the same silicon generation can be pushed at a higher operating point.
The WSE-3 Turbo doubles output while staying at 5nm
The WSE-3T's AI compute performance rose from 125 PFLOPS to 250 PFLOPS per wafer. Memory bandwidth increased from 21.6 PB/s to 43.2 PB/s, on-chip fabric bandwidth from 26.7 PB/s to 53.5 PB/s, and external I/O from 1.2 Tbit/s to 2.4 Tbit/s—all exactly doubled. I/O latency also dropped from 5 microseconds to as low as 2 microseconds.
| Metric (per wafer) | WSE-3 | WSE-3 Turbo |
|---|---|---|
| AI compute performance | 125 PFLOPS | 250 PFLOPS |
| On-chip SRAM | 44GB | 44GB |
| Memory bandwidth | 21.6 PB/s | 43.2 PB/s |
| On-chip fabric bandwidth | 26.7 PB/s | 53.5 PB/s |
| External I/O | 1.2 Tbit/s | 2.4 Tbit/s |
| I/O latency | 5 microseconds | as low as 2 microseconds |
However, the 250 PFLOPS figure is a peak value that the datasheet explicitly labels "sparse FP16"—not real-world application performance. Still, the design clearly doubled both compute and data movement together, without increasing core count or SRAM capacity. Speeding up compute units alone wouldn't improve inference speed if weights and intermediate data can't move fast enough to match.
What enables the higher clock speeds is a new "Wafer-Scale Backpack." It integrates power conversion and direct liquid cooling around the wafer, packing high-speed I/O and control circuitry into a vertical module that connects to a power array at the back of the rack. While the distance between power conversion circuitry and the processor is typically around 50 millimeters on a standard GPU board, CS-4 shrinks this to roughly 0.5 millimeters. According to Cerebras, this reduces power loss on the board and allows twice the power to be delivered to the WSE-3T compared to before, enabling higher clock frequencies.
This isn't a free performance gain, though. Increasing power delivery per wafer also increases the burden on rack-level power intake and heat dissipation. CS-4 integrates direct liquid cooling into the module, but the publicly released five-page datasheet doesn't specify total rack power consumption or cooling water requirements. The claimed up-to-10x throughput-per-watt improvement is, at this point, based on internal benchmarks and projections—users don't yet have enough information to independently verify the calculation.
What does 4,400 tokens/second actually measure?
In a comparison using identical prompts on GPT-OSS-120B, Cerebras reports that CS-4 exceeds 4,400 tokens per second per user, up to 30 times faster than GPU-based systems. What's being measured here is generation speed—how quickly output is returned to a single user. This matters for conversational AI, coding assistants, and agents that repeatedly call tools, where reducing the wait for each response is valuable.
That said, the 4,400 tokens/second figure comes from a head-to-head test conducted by Cerebras itself. The announcement materials don't specify the GPU model, unit count, numerical precision, or batch size used for comparison. Concurrent user count and context length are also unspecified. A footnote even states that actual throughput varies depending on model architecture, context length, precision, and deployment configuration. The "up to 30x" figure should be read as an upper bound demonstrating CS-4's capability—not extended into a fixed performance gap against GPUs in general.
Independent API measurements published by Artificial Analysis as of August 25, 2026 show that gpt-oss-120b (high) running on Cerebras achieved 1,714.6 tokens per second, ranking first among comparison targets. This figure reflects speed measured after the first output token following a 10,000-token input, using the median value over the preceding 72 hours. Even in a public-facing service, Cerebras's characteristic high-speed output is confirmed.
However, it hasn't been disclosed whether this API runs on CS-4. Since 1,714.6 and 4,400 were measured under different conditions, the former can't be used to verify the latter. Cerebras's claim of 1,000 tokens per second on a model with over 10 trillion parameters is also an extrapolation from internal measurements. The model name, number of active parameters, and precision haven't been disclosed. Without knowing the number of wafers required, it's impossible to judge how reproducible this would be in actual operation.
Splitting prefill and decode, rather than replacing GPUs outright
CS-4's new Wafer I/O Module supports RDMA over Ethernet via RoCE v2, along with Direct Wafer Links that connect wafers to each other without going through a switch. This keeps communication latency within and between racks as low as 2 microseconds. Cerebras states that this connectivity can also be used in large clusters handling models with over 50 trillion parameters.
A practical application of this low-latency I/O is splitting inference processing into prefill and decode stages. Prefill processes the entire input prompt at once, making it well suited to parallel computation. Decode, by contrast, generates one token at a time based on previously generated output—here, memory bandwidth for quickly reading model weights matters more than raw compute.
Cerebras has already announced partnerships that hand prefill duties to AMD Helios and AWS Trainium, concentrating decode work on the WSE. The joint configuration with AMD claims up to 5x tokens/s/W and is planned for availability on Cerebras Cloud in the latter half of 2026. The AWS configuration is planned for deployment on Amazon Bedrock.
This combination illustrates both the strengths and limits of the WSE at once. Its 44GB of on-chip SRAM and 43.2 PB/s bandwidth suit fast decode work well, but that doesn't mean a single type of device can be optimally used for everything—including processing long inputs and holding the KV cache for many simultaneous users. By placing GPUs or dedicated ASICs upstream, Cerebras can dedicate its compute resources to fast decode. CS-4's doubled I/O, then, is less about wholesale GPU replacement and more an improvement aimed at combining different accelerators into a single inference service.
A 600MW expansion plan and the manufacturability of Nexus
CS-4 is also the first product built on what Cerebras calls its "Nexus" rack-scale platform. By separating compute, power, and I/O into independent modules, the Wafer-Scale Backpack cuts component count by 50% compared to the previous generation. The company says it has increased assembly automation by 60%, shortening data center deployment time from days to hours.
The reduced part count and increased automation in Nexus align with Cerebras's broader manufacturing expansion. In its Q2 2026 earnings announcement, the company stated that data center capacity either operational or under contract will exceed 600MW by the end of 2027, and that it plans to increase manufacturing capacity more than tenfold within 2026. Through its partnership with Flex, Cerebras has also announced plans to boost CS-3 production capacity roughly sevenfold within the same year.
According to Flex, manufacturing the CS-3 requires special handling, dedicated fixtures, and precise calibration. Factories integrate liquid cooling, verify optical networking, and certify entire racks before shipment. While it's not certain that CS-4's process is identical, Nexus's design—which reduces part count and on-site labor time—should help contain the complexity of supplying wafer-scale machines at volume.
Supply chain choices also differ from GPU racks. Cerebras states it has secured the wafer supply it needs from TSMC and emphasizes that it doesn't rely on HBM, CoWoS, or the 3nm process. Because the WSE places 44GB of SRAM directly on the wafer, it isn't directly exposed to HBM and advanced-packaging shortages. CS-4's supply plan doesn't depend on the components the company itself describes as being in tight supply elsewhere in the industry.
What remains to be judged is real-world operational performance rather than headline peak speeds. Hot Chips 2026 has a session scheduled on August 25 (Pacific time) covering Cerebras's rack-scale design. Post-shipment rack power consumption, pricing, tokens/s/W under concurrent load, and actual volume shipment track record all still need to be confirmed. Once independent organizations reproduce the 4,400 tokens/second figure and these additional numbers become available, it will be possible to judge whether CS-4 can absorb the cost of higher clock speeds and turn low-latency inference into a large-scale business.