Goldman Sachs has forecast that China's sub-7nm wafer supply shortfall will shrink from 92% in 2025 to 34% by 2035. The South China Morning Post (SCMP) reported this on August 24. The calculation implies domestic supply growing to roughly two-thirds of demand, but it rests on the assumption that SMIC will keep expanding advanced-node capacity every year while raising yields from 23% in 2026 to 75% by 2035. That 34% is not an already-visible endpoint — it is a scenario that asks whether advanced-node capacity and good-die yields can be improved in tandem over a full decade.
What a 44-fold multiplier reveals when you work backward from "92% to 34%"
The forecast's endpoint is monthly supply of 410,000 wafers against demand of 619,000 wafers in 2035. That puts the domestic supply ratio at about 66.2%, leaving a monthly shortfall of 209,000 wafers. A "34% shortfall rate" does not mean a 34% self-sufficiency rate — it means China cannot meet roughly one-third of demand through domestic production.
Working backward from the published growth rates and the 2035 figures, advanced-node wafer supply in 2025 comes out to roughly 9,300 wafers per month, against demand of about 128,800 wafers per month, for a supply ratio of about 7.2%. That is broadly consistent with the reported 92% shortfall rate. Since this is derived by working backward from rounded figures, it is not a precise starting value, but it does convey the scale of change the forecast requires.
However, the full original Goldman Sachs report could not be confirmed, and it is not possible to determine whether the "supply" figure in media reports refers to wafer input capacity, good-die-equivalent output, or a figure adjusted for product mix. The 44-fold multiplier in this article assumes the same supply definition was used for both 2025 and 2035; it is not a production figure derived solely from yield improvement.
If supply grows at an average annual rate of 46% over ten years, the monthly wafer count increases roughly 44-fold. Demand, meanwhile, grows at an average annual rate of 17%, or about 4.8-fold. The supply ratio rises about 9.2-fold. In other words, reaching the 34% endpoint is not a matter of gradual catch-up — it requires the reported supply metric to nearly double every single year. Even a delay of a few years would substantially upend the calculation.
The model's twin pillars: capacity expansion and a 75% yield
Goldman Sachs's model assumes SMIC will add 30,000–50,000 wafers per month of advanced-node capacity every year from 2026 through 2031, and 20,000 wafers per month each year from 2032 through 2035. Simply summed, that would bring total added capacity over the decade to 260,000–380,000 wafers per month. But how many wafers can be processed and how many good dies can be extracted from them are two different numbers.
The yield assumption rises from 23% in 2026 to 50% in 2030 and 75% in 2035 — an improvement of 52 percentage points, or roughly 3.26-fold. If defect rates remain high, good-die output will not grow, and per-wafer cost will not fall either. Whether manufacturing conditions can be stabilized, defects reduced, and the same design repeatedly turned into good dies at a high rate is a separate assumption from capacity expansion, and one the model simply asserts.
SMIC's second-quarter 2026 earnings disclosed total production capacity of 1,096,500 wafers per month (in standard logic 8-inch equivalents) and a 93.7% utilization rate, but did not disclose sub-7nm capacity or yield. The total capacity figure is a company-wide number that includes mature nodes, so it cannot be directly compared against the sub-7nm wafer forecast to calculate a ratio.
Capital expenditure for that quarter was $1.8357 billion, with revenue of $3.005568 billion. This confirms that the company operated at high utilization and made substantial capital investments during the quarter, but that alone does not indicate how much room there is for sub-7nm expansion, nor does it corroborate Goldman Sachs's assumed 23% advanced-node yield. The more central a figure is to the model, the harder it is to verify from public financial disclosures.
The wall of DUV multi-patterning and mass-manufacturability
SMIC has reached 7nm-class production without using extreme ultraviolet (EUV) lithography, instead combining deep ultraviolet (DUV) lithography with multi-patterning. Multi-patterning splits a complex circuit into multiple simpler patterns and repeats exposure, deposition, and etching. The more repetitions required, the harder alignment and defect control become, and the longer processing takes.
In its own model published in ASML's 2025 annual report, the company states that moving from DUV multi-patterning to single-pattern EUV can reduce the number of process steps per wafer by about 20%. EUV tools themselves consume large amounts of power. Even so, because fewer subsequent deposition and etching steps are needed across the overall production line, defects, cost, and cycle time are easier to contain. There is a gap between being able to draw fine circuits with DUV and being able to mass-produce competitively high yields of good dies — a gap rooted in process integration.
Equipment restrictions are not limited to a single type of lithography tool. In December 2024, the U.S. Commerce Department's Bureau of Industry and Security (BIS) added export controls on 24 types of semiconductor manufacturing equipment, including lithography tools, and three types of software. In addition to deposition and etching equipment, ion implantation and thermal processing tools are also covered. Metrology, inspection, and cleaning equipment fall within the scope as well. The Netherlands has also placed certain advanced DUV tools under a licensing requirement — though this involves case-by-case review, not a blanket export ban on DUV.
Reaching a 75% yield will require more than higher exposure resolution. It demands measuring variability at each process step, identifying the causes of defects, and keeping equipment running at high utilization. At the same time, it cannot be confirmed from Goldman Sachs's public reporting whether the model factors in mass production of Chinese-made EUV tools. What can be confirmed from public information is only that the model simultaneously assumes major yield improvement and capacity expansion. The 75% yield assumption and questions of equipment procurement or domestic localization cannot be treated as part of the same causal chain.
"Sub-7nm" does not mean "leading-edge" in 2035
The sub-7nm category is a convenient way to measure how far China's domestic supply base can expand, but the technology frontier itself is not standing still. TSMC began mass production of 7nm in 2018 and moved to EUV-based N7+ mass production in 2019. It further began 2nm mass production in the fourth quarter of 2025, with A14 mass production planned for 2028.
Given this time gap, even if China can supply 66% of sub-7nm wafer demand domestically by 2035, that would not mean it has caught up to the leading edge at that point. Since TSMC plans to mass-produce A14 by 2028, the scale of 7nm production and the degree of catch-up to the 2035 leading edge need to be measured separately. Even while lagging the leading edge, expanding stable supply of 7nm-class chips still serves a purpose in meeting targeted domestic demand within China.
Node names assigned by manufacturers are also not a standardized measure implying equal density and performance for the same number. Comparing SMIC's "7nm" to TSMC's N7 by name alone cannot yield a meaningful figure for "years behind." Goldman Sachs's 34% is a number that measures the shortfall relative to domestic demand — it is not a number that converts a technology gap into a single year figure.
Goldman Sachs has also separately estimated that China's semiconductor self-sufficiency rate, measured by volume, rose from 38% in January 2010 to about 70% by June 2026. This 70% figure and the roughly 66% domestic-supply ratio for advanced-node wafers in 2035 are not contradictory: the former counts the volume of the entire semiconductor sector including mature nodes, while the latter counts sub-7nm wafer supply and demand specifically.
The company itself notes that self-sufficiency falls if measured by value rather than volume, because producing large volumes of small, mature-node chips raises the unit count while continued imports of expensive AI accelerators and high-bandwidth memory keep value-based dependence intact. Wafer count likewise does not represent computing power — even from a single wafer, the number of chips obtained and their performance vary depending on die size, yield, design, and packaging method.
So when reading the 34% figure, it is essential to fix exactly what it is a shortfall of. It refers to sub-7nm wafers for which there is demand within China — not chip revenue, and not AI computing capacity. Losing sight of this distinction risks either mistaking an improvement in the domestic supply chain for a shift in technological supremacy, or, conversely, underestimating the expansion of domestic supply by focusing only on the gap with the leading edge.
2030 as a checkpoint for capacity expansion and the 50% yield assumption
The forecast faces an initial test well before 2035. Goldman Sachs expects SMIC's advanced-node yield to rise to 50% by 2030 and China's semiconductor capital expenditure to reach $82 billion that same year. If yield improves from 23% to 50% and expanded production lines maintain consistent quality, part of the model's capacity-expansion assumption will be validated. But if capital expenditure rises while good-die supply at advanced nodes fails to grow accordingly, the 34% target will recede further.
Another variable is demand. The model assumes sub-7nm wafer demand grows at an average annual rate of 17% over the decade. If AI investment surprises to the upside, the projected monthly demand of 619,000 wafers could swell even further, and the shortfall rate would rise even if supply proceeds as planned. Conversely, if demand growth slows, the domestic supply ratio could rise even without stronger improvements in manufacturing technology — which is precisely why a rising self-sufficiency rate cannot simply be equated with rising manufacturing competitiveness.
What should be checked in 2030 is not SMIC's company-wide capacity, but specifically how good-die output at sub-7nm nodes is growing. Layering that against advanced-DUV export licensing, procurement of metrology and inspection equipment, and the pace at which TSMC brings A14 and beyond into mass production would make it possible to track the domestic supply base and the technology frontier as separate threads. Rather than waiting for the 2035 endpoint, disclosure of node-specific capacity and yield data would allow the two central assumptions — capacity expansion and a 50% yield — to be verified independently.