In the first half of 2026, Chinese AI chip companies posted broad-based revenue growth: Cambricon's sales reached 5.996 billion yuan, up 108.13% year-on-year; Moore Threads hit 1.736 billion yuan, up 147.42%; and Biren posted 1.236 billion yuan, a staggering 1,998% increase. Around the same time, NVIDIA's revenue from China-headquartered customers for the full fiscal year ending January 2026 (FY2026) came to just 9.1% of total company sales, and its guidance for the third quarter of fiscal 2027 excluded China data center compute revenue entirely. Demand, capital, and policy all appear aligned on China's side. Yet the SCMP reported in August 2026 that China's leading large language model developers are still using NVIDIA chips to train their most advanced models. This simultaneous occurrence of surging Chinese chip revenue and continued dependence on NVIDIA cannot be explained by raw chip performance differences alone.
Soaring Chinese revenue, and a company that doubled sales after losing China
NVIDIA booked a $4.5 billion charge related to H20 sales to China, but the revenue it was actually able to recognize afterward under license was only about $60 million—meaning the charge was 75 times larger than the revenue it eventually realized. Both figures appear side by side in the same Form 10-K for fiscal year ending January 2026. In April 2025, the U.S. government required licenses for H20 exports to China, and NVIDIA booked the $4.5 billion in the first quarter as a valuation of inventory and purchase commitments. Some licenses were granted in August of that year, and the resulting revenue came to $60 million. The $4.5 billion charge covered both inventory valuation and purchase obligations, and is accounting-wise distinct in nature from the revenue realized afterward.
In the same 10-K, NVIDIA states its position candidly: as of the end of fiscal 2026, it had effectively been shut out of competition in China's data center compute market, and this exclusion helped expand the developer and customer ecosystems of its competitors on a global scale. Jensen Huang made a similar point in October 2025, in a conversation at a Citadel Securities event: "We went from 95% market share to 0%. No policymaker could think that's a good idea." The company's own disclosure and its CEO's remarks point in the same direction.
Yet the company's financial results moved in the opposite direction. Revenue for the second quarter of fiscal 2027 (ended July 26, 2026) reached $96.2 billion, up 106% year-on-year, with the data center segment posting $89.0 billion, up 117%. Data center now accounts for 92.5% of total revenue. And the guidance for the third quarter—$108 billion—explicitly assumes zero China data center compute revenue. A quarterly forecast that treats one of the world's largest AI chip markets as zero still projects sales higher than the previous quarter.
The drop in China's share of revenue is also easy to misread if you only look at the numerator. NVIDIA's revenue from customers headquartered in China (including Hong Kong) doubled from $12.33 billion in fiscal 2024 to $25.048 billion in fiscal 2025, then fell to $19.677 billion in fiscal 2026—a roughly 21% decline in absolute terms.
Meanwhile, total company revenue grew from $130.497 billion to $215.938 billion, a 1.65x increase. As a result, China's share of total revenue moved from 20.2% to 19.2% to 9.1%. Half of that final 9.1% figure is being driven by the expanding denominator, not by China revenue itself.
This "China revenue" figure is tallied by customer headquarters location, not by the value of chips that physically entered China. The same 10-K estimates that 76% of data center revenue booked to Taiwan-headquartered customers in fiscal 2026 was ultimately attributable to end customers outside Taiwan. Regional revenue tables list where customer companies are headquartered—they are not a map of where computing resources actually reside.
Six stages of regulation, and a product that changed each time
Between October 7, 2022, and January 13, 2026, U.S. export controls on AI chips to China passed through at least six turning points. Of the six stages listed in the table, four represent tightening and two represent easing. Each time controls tightened, NVIDIA released a China-specific product that fell just under the new threshold, only for the next round of tightening to close that loophole. Beyond these six stages, additional targeted tightening measures were layered in separately—such as the January 2025 strengthening of advanced semiconductor rules and the August 2025 elimination of the exemption for foreign-owned foundries.
| Date | Regulatory action |
|---|---|
| 2022-10-07 | BIS enacts export controls on advanced computing and semiconductor manufacturing equipment to China. A100 and H100 fall under the rules |
| 2023-10-17 | BIS publishes revised rules, adding performance density as a criterion alongside total processing performance, and removing interconnect bandwidth as a criterion |
| 2024-12-02 | Third round adds HBM (new ECCN 3A090.c), 24 types of semiconductor manufacturing equipment, and 3 types of software. Over 140 entities added to the Entity List |
| 2025-04-09 | U.S. government notifies NVIDIA that H20 exports to China require a license. NVIDIA discloses a charge of up to approximately $5.5 billion |
| 2025-05-13 | Commerce Department announces withdrawal of the AI Diffusion Rule (published January 15, 2025, scheduled to take effect May 15) |
| 2026-01-13 | BIS revises license review policy, subjecting H200 and AMD MI325X and equivalents to case-by-case review |
Of the six rows in the table, the most significant shift in regulatory design came with the October 17, 2023 revision. The original 2022 rules applied two separate conditions together: total processing performance exceeding a certain threshold, and chip-to-chip interconnect speed of 600 GB/s or higher. This allowed a design that kept computational scale intact while lowering interconnect speed below the threshold to escape regulation entirely—which is exactly what NVIDIA's A800 and H800 did.
The following year's revision closed this loophole using a second metric: performance density. Measuring computing performance per unit of die area makes it impossible to hide a high-density compute chip simply by throttling its interconnect. This is the point at which the regulatory language shifted from "what it connects to" to "how densely packed it is."
The third round, on December 2, 2024, expanded the scope beyond compute chips to memory semiconductors, manufacturing equipment, and software. Using the newly created ECCN 3A090.c, it targeted HBM with bandwidth density exceeding 2 GB/s per square millimeter—a threshold that every HBM product currently in production exceeds. Full compliance was required by December 31 of that year. From China's perspective, even as it became possible to design compute chips domestically, the supply channel for the memory stacked alongside them simultaneously narrowed.
The back-and-forth didn't end there. On July 15, 2025, NVIDIA announced it had received assurances from the U.S. government that H20 sales to China could resume, and the Commerce Department began issuing licenses in August. Reports indicated a condition requiring NVIDIA to remit 15% of H20 China sales revenue to the U.S. government. But two months later, on September 17, Bloomberg reported that China's Cyberspace Administration had instructed domestic companies to halt orders for and testing of NVIDIA's RTX Pro 6000D.
The BIS announcement on January 13, 2026 specified three conditions: that global production capacity for U.S. customers not be reduced, that Chinese purchasers implement export control procedures including customer vetting, and that products undergo independent third-party testing within the U.S. The following day, H200 exports to China were formally approved, with reports adding that China-bound shipments could not exceed 50% of sales volume to U.S. customers, and that H200 units re-imported for U.S. testing would face a 25% import tariff—though neither of these two conditions appears in the BIS announcement itself.
Twenty years for CUDA to become the standard, and the person-months needed to switch away from it
By the time export controls began in October 2022, NVIDIA's software assets already represented 15 years of accumulated work. CUDA was announced alongside the GeForce 8800 GTX (G80) in November 2006, with the public SDK release following in February 2007. NVIDIA itself referred to this at GTC 2026 as "20 Years of CUDA," placing the starting point at 2006.
What the G80 did was eliminate the dedicated vertex-shader and pixel-shader pipelines and unify 128 shader processors into a single group of programmable compute processors. This redesign—replacing graphics-only fixed-function circuitry with general-purpose computing units—became the foundational premise for the idea of running computation on GPUs. At the time, the primary use case was scientific and technical computing; deep learning was not yet on the horizon.
The turning point came in 2012. Alex Krizhevsky and colleagues' AlexNet achieved a top-5 error rate of 15.3% on ImageNet (ILSVRC-2012), far outpacing the second-place result of 26.2%.
Training was done on two consumer GeForce GTX 580 cards—not dedicated data center hardware, but off-the-shelf gaming GPUs available at retail. NVIDIA cites this as the starting point of its own investment in AI hardware.
From here, NVIDIA began stacking layers on top of CUDA. In September 2014, it released cuDNN, a library of deep learning primitives, distributing pre-optimized components for frequently used operations like convolution and normalization. At GTC in May 2017, NVIDIA unveiled the Volta architecture and Tesla V100, which included the first-generation Tensor Core. This unit, which processes matrix multiply-accumulate operations in dedicated circuitry, went on to become the computational foundation that major training frameworks would incorporate as a standard acceleration pathway.
CUDA as the foundation, cuDNN as the components, Tensor Core as the dedicated circuitry—these three layers were each built in different years, out of different necessities. NVIDIA's 10-K states that developers using CUDA and its software tools worldwide number more than 7.5 million. Jensen Huang cited a figure of 5 million at Computex in June 2024.
How this accumulated stack translates into switching costs is evident in testimony from migration efforts that the SCMP reported on August 10, 2026. According to one Beijing-based engineer involved in Ascend migration, models like DeepSeek, which are fully open-sourced down to their source code, along with their distilled versions, can be trained on domestic chips with just 2-3 additional engineers working for about a month. But for models like Moonshot AI's Kimi K3, which release only weights, the additional work required can call for a team of roughly 10 engineers over more than 6 months. In person-month terms, that's roughly 2-3 person-months versus over 60—a gap exceeding 20-fold. Using the midpoint of 2.5 person-months, the gap is roughly 24-fold.
In the same report, James Wang, who develops AI models at a research institute affiliated with a Shanghai university, said that CUDA code does not run directly on Ascend and requires extensive rewriting, and that migrating existing workflows can take at least 50% more time and cost.
Why does the disclosure format make such a big difference? Models whose source code is fully public reveal the training loop, the parallelization approach, and the data pipeline—all of which can be read directly. The migrating team simply needs to replace these procedures with equivalent Ascend calls.
For models where only the weights are released, the training procedure that produced those weights must be reconstructed from scratch. This means inferring which operations were run at which precision, in what order, and with what memory layout, then building an implementation on Ascend that reproduces equivalent numerical behavior. CUDA's twenty years of accumulated tooling is, in effect, an inventory of off-the-shelf components that eliminates the need for this kind of guesswork. The fact that migration is further along for inference than for training reflects the same logic—inference relies on a fixed computation graph, requiring far fewer procedures to be reproduced compared to training.
Why is a company posting +1,998% revenue growth still unprofitable?
Biren Technology's revenue for the first half of 2026 came to 1.236 billion yuan, up 1,998% year-on-year. This figure was confirmed in the company's interim results filed with the Hong Kong Stock Exchange on August 28, 2026, with gross margin at 42.7% (up 10.8 percentage points year-on-year) and net loss narrowing 76.4% to $56.1 million. Even with revenue growth of 20-fold, the company's bottom line remains in the red. Notably, in a preliminary interim results announcement filed with the Hong Kong Stock Exchange on August 17, the company had indicated a growth range of 1,852% to 2,107%. The widely circulated "2,107%" figure was the upper end of that projected range, not the actual confirmed result.
Comparing the three companies' figures side by side reveals that the magnitude of revenue growth and current financial health are two separate matters.
| Company | H1 2026 revenue | YoY change | Profit/loss |
|---|---|---|---|
| Cambricon (688256.SS) | 5.996 billion yuan | +108.13% | Net profit attributable to parent shareholders: 2.311 billion yuan (+122.61%) |
| Moore Threads (688795.SS) | 1.736 billion yuan | +147.42% | Net loss of 11.5631 million yuan (narrowed 95.73%) |
| Biren (6082.HK) | 1.236 billion yuan | +1,998% | Net loss of $56.1 million (narrowed 76.4%) |
Only Cambricon is profitable; the other two remain in a loss-narrowing phase. For all three companies, the source of revenue growth traces back to domestic demand capture. Procurement rules that exclude foreign-made accelerators from government-funded projects translated directly into orders for these companies.
Cambricon's stock briefly surged to 1,620 yuan in late June 2026, closing at 1,595.55 yuan and making it the first company on the STAR Market to reach a market capitalization of 1 trillion yuan. Moore Threads closed at 600.50 yuan on its debut day on the STAR Market on December 5, 2025—425.46% above its offering price—with cloud AI compute products accounting for 97.5% of first-half revenue. Biren listed on the Hong Kong Stock Exchange main board on January 2, 2026, with institutional demand reaching about 26 times the offered shares and retail demand reaching approximately 2,348 times.
Huawei, as a private company, does not publish results in the same format, but its AI chip business revenue is projected to grow from roughly $7.5 billion in 2025 to about $12 billion in 2026—a surge comparable to the three listed companies. However, its design philosophy differs.
At Huawei Connect on September 18, 2025, Eric Xu unveiled Ascend's three-year roadmap, placing the Ascend 950PR in Q1 2026 and the 950DT in Q4 of the same year. The 950DT is specified to carry 144GB of Huawei's own HiZQ 2.0 HBM, with 4TB/s memory bandwidth and 1 PFLOPS at FP8. The design philosophy shows up not in individual chip specs but in how they're bundled together—the Atlas 950 SuperPoD is described as combining up to 8,192 units of the 950DT to deliver 8 EFLOPS at FP8. If you can't win on per-chip performance, the choice becomes to make up for it through sheer numbers connected together.
On the software side, Huawei announced in August 2025 that it would open-source CANN (Compute Architecture for Neural Networks), with plans to publish all operators on GitCode by the end of September that year. On April 24, 2026, the day DeepSeek released a preview of V4, Huawei announced that Ascend 950PR and 950DT supported V4 on the same day.
Even so, exactly how far foreign vendors have been pushed back in the Chinese market doesn't resolve into a single number. Estimates of foreign vendors' share of China's AI chip market in 2025 diverge sharply: IDC's research, as reported by Reuters, put it at 59%, while TrendForce's forecast, as reported by SCMP, put it at 34%—a 25-point gap. The former appears to combine NVIDIA's 55% and AMD's 4% based on card shipment volume, while it's unclear from the original source whether the latter is based on shipment units or value. When the tallying metric and the population being measured differ, even estimates for the same market in the same year can swing this widely. Any single figure for domestic market share is meaningless without specifying which survey and which metric it's drawn from.
The other ceiling: HBM
Huawei's production target for the Ascend 910C in 2026 is reportedly around 600,000 units, but domestic HBM producer CXMT's production capacity remains capped at roughly 2 million stacks annually—enough for only 250,000 to 300,000 Ascend 910C equivalents. The target is roughly double the available supply. This conversion is based on an estimate SemiAnalysis presented as of September 8, 2025; CXMT reportedly began sample shipments of HBM3 to Huawei from mid-2025, aiming for mass production within the year, according to reports as of January 2026—so the situation may be evolving.
Comparing this to the logic-side capacity paints a clearer picture of where the true constraint lies. SMIC's sub-7nm production capacity is projected to expand from a monthly output of 45,000 wafers at the end of 2025, to 60,000 in 2026, and 80,000 in 2027, and one analysis suggests that mass-producing Ascend dies would require at most 20,000 wafers per month. If this holds, logic capacity is not the bottleneck.
However, the same N+2 line is being contested by Cambricon, Biren, Moore Threads, MetaX, Alibaba's T-Head, Baidu Kunlunxin, and Huawei HiSilicon—all competing for wafer allocation. SMIC's overall utilization rate reportedly reached 93.7% as of Q2 2026, indicating that total production capacity, including the N+2 line, is already tight. Under this view, domestic chip volume is also constrained on the logic side. The conclusion changes depending on whether you look at Huawei alone or the domestic chip design industry as a whole. Either way, HBM remains the shared ceiling.
Why does memory determine the production volume of compute chips? AI accelerators are structured with HBM stacked around the compute die within a single package—no matter how many compute dies are produced, the product cannot ship unless enough HBM stacks are available to match. The Ascend 910C is said to carry 128GB of HBM per unit, and without a corresponding supply of stacks, the package cannot be completed. Compute-side and memory-side production volumes don't multiply together—they're bottlenecked by whichever is smaller.
That HBM was precisely what the BIS regulation of December 2, 2024 targeted. By setting the threshold at bandwidth density exceeding 2 GB/s per square millimeter, every HBM product currently in production ends up above the regulatory line. What followed was a rush to stockpile. According to SemiAnalysis estimates, Samsung supplied 11.4 million HBM stacks to China, with 7 million of those concentrated in the single month between the regulation's announcement and its enforcement.
Combined with other suppliers, total shipments of 13 million stacks amount to the equivalent of 1.6 million Ascend 910C packages. China's AI chip industry now finds itself consuming down the inventory it rushed to accumulate right before controls took effect, while waiting for domestic HBM production to ramp up. The same set of constraints comes up in discussions of what limits Cambricon: reports of yield around 20% for the largest die on SMIC's 7nm process, combined with its dependence on SK hynix and Samsung for HBM procurement.
Equipment makers where China's share is falling, and those where it's rising
Tokyo Electron's revenue share from China fell from 49.9% in the April-June 2024 quarter to 30.4% in the April-June 2026 quarter, while TOWA's rose from 35.9% to 40.9% over roughly the same period—showing that the ripple effects of export controls on Japanese semiconductor equipment makers are far from uniform.
| Company | Prior period | Latest period | Direction |
|---|---|---|---|
| Tokyo Electron (quarterly, China revenue share) | 49.9% (Apr-Jun 2024) | 30.4% (Apr-Jun 2026) | Declining |
| SCREEN Holdings (full-year, China revenue share) | 42% (FY ended March 2025) | 38% (FY ended March 2026) | Declining |
| TOWA (full-year, by destination) | 35.9% (FY ended March 2025) | 40.9% / ¥22.23 billion (FY ended March 2026) | Rising |
These three companies' figures should not be read as pointing in the same direction. Tokyo Electron and SCREEN focus primarily on front-end equipment, while TOWA focuses on back-end packaging equipment—their product mixes differ. The reporting periods also differ in granularity: Tokyo Electron's is quarterly, while the other two are annual.
Even so, the divergence in direction is real. Tokyo Electron's China revenue share for the full fiscal year ended March 2026 was 34.1%, which is consistent with a weighted average of 34.06% derived from its quarterly shares weighted by quarterly revenue. TOWA's China revenue also grew in absolute terms, from ¥19.21 billion to ¥22.23 billion.
This asymmetry reflects what export controls do and don't stop. Front-end equipment for advanced logic sits at the center of export controls, and Chinese investment has shifted from leading-edge to mature nodes accordingly. Back-end processes like packaging and testing, however, face a comparatively looser regulatory net—yet equipment is still needed both to stack HBM and to connect chiplets. SCREEN Holdings explained at its earnings briefing for the fiscal year ended March 2026 that while China's memory investment had traditionally centered on legacy general-purpose products, demand for high-performance segments including HBM has been growing, creating new opportunities for the company. SCREEN's Mr. Goto said the company estimates the impact—should the MATCH Act pass and be enforced—at roughly 10% to 15% of China revenue.
There is a structural irony here. Even though blocking China's domestic HBM production is one of the stated goals of U.S. export controls, SemiAnalysis points out that the advanced equipment needed to form TSVs (through-silicon vias)—a critical step in HBM manufacturing—remains accessible to CXMT through Japanese suppliers. Japan's equipment companies find themselves standing on both sides: restricting China's AI compute capacity on one front, and supporting it on the other. Making up in back-end business what's lost on the front-end is rational from a corporate standpoint, but looks like a loophole from a regulatory design perspective. For investors watching domestic semiconductor equipment stocks, the era when "China exposure" could be summarized in a single figure is over.
Conditions for the two walls to fall, and three switches to watch next
In 2026, China also saw an unusual reversal: the U.S. willing to sell, and China declining to buy. ByteDance and Tencent reportedly each received their first shipments of NVIDIA H200 units in August 2026. These imports required individual approval from China's National Development and Reform Commission (NDRC), and reports suggest Beijing prefers to keep much of this hardware outside mainland China, in places like Hong Kong. Even after clearing the export control hurdle, another gate stands on Beijing's side.
Behind this lies procurement-ratio regulation rather than any publicly stated self-sufficiency target. In August 2025, the government required state-owned data center operators to source at least 50% of their chips domestically; in November of the same year, it excluded foreign-made accelerators entirely from government-funded projects, mandating removal for any project less than 30% complete. Then in June 2026, reports emerged of a plan for a national AI data center network, investing 2 trillion yuan ($295 billion) over five years, requiring 80% or more domestic sourcing of technology, with the NDRC leading integration by 2028. The three figures—50%, full exclusion, and 80%—each apply to a different scope of facilities. Lining them up under the single label of "domestic production ratio" obscures which policy stage is actually in effect.
Whether the two walls will actually fall can be judged by tracking the two indicators traced in this article. On the software side, the question is how close the effort to migrate weight-only-released models to Ascend can get to the open-source-model figure—currently 10 engineers over more than 6 months, versus 2-3 engineers over 1 month for open models. Open-sourcing CANN is a step in that direction, and the key things to watch are whether the torch_npu adapter can keep pace with and remain stable alongside changes to PyTorch itself, and whether openly published models can run without Huawei-specific tuning. On the memory side, the question is whether CXMT's HBM3 reaches mass production within 2026 and pushes past the estimated 2-million-stack annual ceiling. The Ascend 910C's target of 600,000 units hinges entirely on this single factor, for better or worse.
Three switches could shift things in the short term. The first is U.S. approval of the B30A—developed as a successor to the H20, this Blackwell-family product is said to offer roughly half the compute performance and memory bandwidth of the B300, but export approval has not yet been granted. The second is how remote access is treated: Chinese AI companies are renting compute resources from data centers in Southeast Asia to access controlled chips, and as Cassia King of the Institute for AI Policy and Strategy has pointed out, U.S. export controls target physical chips, not remote access. The Remote Access Security Act, meant to close this gap, passed the House in January 2026 but has not yet passed the Senate. The third is the fate of the MATCH Act—as SCREEN's impact estimate suggests, the flow of equipment and maintenance services will shift depending on whether and how it is enacted and enforced.
CUDA's twenty years cannot simply be purchased by anyone willing to spend twenty years' worth of money. Ever since AlexNet ran on two off-the-shelf GTX 580 cards in 2012, frameworks, textbooks, and adoption case studies have all been built on top of CUDA.
Even if China closes that gap, it doesn't need to retrace the same twenty-year path. There remains a route of advancing use cases from inference to training step by step, timing the migration to align with when domestic HBM supply catches up. Just as DeepSeek V4 achieved same-day inference support on Ascend, migration moves faster the more openly a model's format is released. The more Chinese model developers commit to open-sourcing their code, the faster migration to domestic chips accelerates—a dynamic that the designers of these export controls likely never anticipated.