China has already brought a 7nm-class smartphone SoC to market without using EUV lithography equipment. Even so, Frank Rohmund, President and CEO of ZEISS Semiconductor Manufacturing Technology (ZEISS SMT), which supplies EUV optics to ASML, told DIGITIMES that advanced packaging cannot fully close the manufacturing-process advantage that EUV provides, even as it improves performance gains. The question is not whether a chip can be made once. It is whether multi-patterning DUV can be extended to even finer nodes while still yielding enough good chips at a competitive cost, sustainably, in volume.
7nm Was Commercialized Without EUV
TechInsights disassembled the Huawei Mate 60 Pro and confirmed that the Kirin 9000S was manufactured using SMIC's second-generation 7nm process, "N+2." The Kirin 9000S is a full SoC with features such as embedded SRAM, representing the most advanced logic that a Chinese foundry has commercialized without EUV. Therefore, the claim that "commercial chips are impossible without EUV" contradicts a confirmed product.
However, reaching 7nm does not mean the same approach can remain profitable at even finer nodes going forward. TechInsights' analysis indicates that SMIC used multi-patterning. Advanced immersion DUV uses 193nm light. Even so, by splitting one complex circuit layer into two or more simpler patterns and repeating exposure and processing, fine features can still be created. As the number of splits increases, so do the number of masks and process steps, and precisely overlaying separately drawn patterns also becomes more difficult.
Rohmund's warning is directed at the burden that increases during mass production. According to an explanation published by DIGITIMES on July 21, 2026, ZEISS acknowledged that advanced packaging can improve overall chip performance, but stated that it cannot fully replace the process-level advantages that EUV provides. Even if packaging connects multiple dies in close proximity to boost system performance, the complexity of the lithography process used to make each individual die remains.
More Masks and Overlay Work With Multi-Patterning
In its 2025 Annual Report, ASML explains that moving from complex multi-patterning with DUV immersion systems to single-exposure EUV can reduce the number of masks and process steps. Shorter process flows mean fewer opportunities for defects to be introduced, improving yield and scalability toward advanced logic and memory. EUV's value lies both in its ability to draw fine lines and in simplifying the process needed to reproduce those lines repeatedly on a mass-production line.
According to the process model presented in ASML's 2025 Annual Report, single-exposure EUV reduces the number of process steps per wafer by roughly 20% compared to multi-patterning DUV. However, EUV equipment itself consumes more power than DUV. The estimate suggests that when etching and deposition steps after exposure are included, the reduction in process steps could lower total power and chemical usage per wafer. In commercial mass production, it is not the exposure tool's spec sheet but the entire process required to obtain a single good chip that determines cost.
The light that creates this difference has a wavelength of 13.5nm. According to ZEISS, because EUV light is absorbed by air and glass, exposure tools must guide the light using mirrors inside a vacuum. The optical system that ZEISS supplies for ASML's scanners consists of approximately 35,000 components, stands about 1.5m tall, and weighs about 3.5 tons. Mirror surfaces are coated with more than 100 layers of thin film, stacked with atomic-level precision, to minimize light loss.
The supply chain is also extremely narrow. ASML is the only company in the world capable of manufacturing EUV lithography systems, and ZEISS provides the core reflective optics at their heart.
That said, leading-edge fabs are not abandoning DUV entirely in favor of EUV alone. ASML explains that critical layers with the smallest features are drawn using EUV, while layers with larger features continue to use DUV. Competitive differences are not determined solely by the number of EUV systems owned, but appear across the entire production line—how the appropriate exposure method is assigned to each layer, and how metrology and correction are integrated throughout.
Regulations Expanded From EUV to Advanced DUV
On June 30, 2023, ASML explained that sales of EUV systems were already restricted. Starting September 1 of the same year, government authorization also became required to export advanced immersion DUV systems—the TWINSCAN NXT:2000i and later models—outside the Netherlands. Chinese manufacturers cannot introduce EUV, and even their procurement of the advanced DUV systems used as an alternative is subject to review.
On September 7, 2024, the Dutch government further expanded the list of advanced semiconductor manufacturing equipment subject to authorization. The list includes certain DUV lithography systems. At the same time, the government has explicitly stated that the system involves case-by-case review for each export destination, and is not a blanket embargo. Rather than drawing a uniform line on which equipment is available, the mechanism gives the government control over which model is shipped to whom.
This authorization system does not mean China's existing production lines will stop immediately. However, it does create uncertainty around the outlook for adding new equipment or increasing capacity during process upgrades. Because multi-patterning requires passing wafers through equipment more times, the more complex the process becomes, the greater the dependence on lithography capacity and equipment uptime. The absence of EUV and the constraints on procuring advanced DUV thus overlap within the same mass-production plan.
Huawei Compensates for Performance Without Relying Solely on Miniaturization
On May 25, 2026, Huawei announced its "Tau Scaling Law," which reduces time constants rather than relying solely on geometric miniaturization. It is a concept for jointly optimizing everything from devices to circuits, chips, and systems, aiming to reduce wiring delay and communication delay. Huawei plans to launch its first Kirin chip adopting LogicFolding—which restructures the physical boundaries of circuit layout—in fall 2026, and is targeting transistor density equivalent to a 1.4nm process by 2031.
This is a future roadmap that Huawei has set forth, not a statement that a 1.4nm manufacturing process has been achieved. LogicFolding is a design-level answer aimed at improving wiring and processing efficiency within limited manufacturing conditions. If it works well, it can extend the performance obtainable even from the same process. That said, it does not eliminate the front-end process burden that determines die area, power consumption, and manufacturing cost.
Node names such as "7nm" and "1.4nm" also do not represent the same dimension measured directly from part of a transistor. TechInsights determined the Kirin 9000S to be SMIC's 7nm generation based on factors such as interconnect pitch, whereas the metric Huawei used for its 2031 target is transistor density. These two figures cannot be directly converted into a generational gap, and the latter has not yet been verified in a shipped product.
The fall 2026 Kirin will provide material for comparing these two approaches in an actual product. Once Huawei's disclosed performance improvements are combined with chip area, power consumption, and shipment volumes, it will become possible to judge how far design and system-level ingenuity can compensate for the absence of EUV. The validity of ZEISS's warning should be measured not by the day a chip was made, but by the day that product could be brought to market in sufficient volume and at a competitive cost.