China's Institute of Microelectronics, part of the Chinese Academy of Sciences, has reportedly established a gate-all-around (GAA) transistor development method targeting sub-3nm generations without relying primarily on extreme ultraviolet (EUV) lithography, according to a DIGITIMES report published on September 17, 2026. The report states that transistors fabricated using deep ultraviolet (DUV) lithography demonstrated an on-off current ratio exceeding 500,000.
For China, which cannot access EUV equipment, research combining GAA's superior gate control characteristics with existing DUV infrastructure makes strategic sense, and if the results scale to circuit level, the implications would be significant. However, what can be confirmed from public information is limited to the demonstration of a promising device development method. It cannot yet be said that performance, density, and yield have been proven at the level of an actual 3nm-class chip.
What a Ratio of 500,000 Does and Doesn't Prove
The on-off ratio is the on-state current divided by the off-state leakage current when a transistor switches. A ratio of 500,000 means the current levels in the two states differ by more than 500,000-fold. It's an important metric for measuring how clearly a device can distinguish between on and off states as a digital switch.
However, this ratio is determined by the combination of numerator and denominator. A high value can result from a large on-current combined with a sufficiently small off-current—or conversely, from a small on-current combined with an even smaller off-current.
Therefore, the ratio alone doesn't reveal how fast the transistor can charge and discharge, at what voltage it operates, or how much current it can drive per unit width.
The logic density figure of 137.8 MTr/mm² cited by Wccftech, along with comparisons to "TSMC's 5nm-class" nodes, are not measured values published by the Chinese Academy of Sciences or SMIC. They are estimates calculated by an account on X (formerly Twitter) based on assumed standard cell dimensions. While theoretical density can be calculated by assuming cell width and height, actual utilization in real products varies depending on cell types, blank areas, power routing, and timing constraints. These estimates cannot be treated as effective transistor density figures.
Why GAA Could Expand DUV's Design Margin
In GAA structures, the gate electrode surrounds a thin sheet- or wire-shaped channel. Compared to FinFET, which controls the channel from three sides, GAA can apply the electric field more efficiently, making it easier to suppress the short-channel effect—the increase in leakage current that occurs when gate length is shortened.
By adjusting nanosheet width and the number of stacked layers, it's also possible to tune the channel area through which current flows, without significantly increasing the planar footprint.
This property doesn't mean DUV itself achieves resolution performance equivalent to EUV. Rather, by improving electrical characteristics on the transistor structure side, there is potential to maintain required performance while allowing some margin in planar dimensions and design rules. This represents an approach that compensates for performance through three-dimensional structure, rather than relentlessly shrinking line widths formed by exposure.
The Institute of Microelectronics has peer-reviewed research supporting this direction. In 2023, the institute fabricated FishboneFET, which retains a protruding silicon structure, and TreeFET, which has multiple branches, reporting structures that increase channel area within the same planar projection area. The research also addressed the difference in drive current between n-type and p-type devices, as well as threshold voltage control. The paper was published in IEEE Electron Device Letters, DOI 10.1109/LED.2023.3294545.
In a separate 2025 study, the institute applied a low-temperature ozone quasi-atomic-layer treatment before gate formation in GAA nanosheet CMOS. According to the institute, this reduced interface state density by two orders of magnitude, achieved a subthreshold swing of 60.3mV/dec, decreased off-current by 66.7%, and increased on-current by more than 20%. This paper was also published in IEEE Electron Device Letters, DOI 10.1109/LED.2024.3524259.
These two results show that the Institute of Microelectronics has been continuously researching GAA device structures, interfaces, and n-type/p-type integration. However, it cannot be confirmed that this is the same technology as the device reported in September 2026. Past peer-reviewed papers cannot be treated as material to supplement the measurement conditions behind the newly reported "500,000" figure.
Beyond the Transistor: Contacts and M0 Remain Challenges
The area of advanced logic is not determined by gate length alone. After devices are formed in the front-end-of-line (FEOL) process, the middle-end-of-line (MEOL) process connects the source, drain, and gate to interconnects. Further, the back-end-of-line (BEOL) process carries signals and power within and between cells across multiple wiring layers.
Even if GAA improves FEOL electrical characteristics, it doesn't necessarily follow that contact holes and the bottom metal layer M0 can be scaled down at the same rate. Thinning contacts increases contact resistance, and thinning metal interconnects increases wiring resistance. Narrowing wire spacing also increases parasitic capacitance, contributing to signal delay.
Furthermore, as multiple exposure and alignment steps are repeated, the risk of vias misaligning with lower-layer wiring increases, as does the possibility that localized defects prevent circuits from functioning correctly.
Standard cell height is constrained not only by the number of GAA sheets but also by the number of routing tracks, M0 pitch, power rails, and design rules concerning cell boundaries. In other words, a significant gap remains—involving contacts and interconnects—between fabricating a single high-performance transistor and arranging billions of them into a functioning, high-density circuit.
This report does not clearly define whether "3nm-equivalent" refers to device performance, design rules, or logic density.
The difference from commercial nodes can be seen in Samsung's explanation when it announced initial mass production of 3nm GAA in 2022. Compared to its own 5nm process, the company stated that at the same performance and complexity, power consumption could be reduced by up to 45%; at the same power and complexity, performance could be improved by up to 23%; and at equivalent design, area could be reduced by 16%.
These are maximum figures published by Samsung itself and cannot be directly compared to the Chinese Academy of Sciences device. Nevertheless, this illustrates that a commercial "3nm" node is not simply a transistor dimension—it is a concept encompassing power, performance, and area (PPA), as well as design infrastructure and mass-production technology.
For research results to reach the same stage, single-transistor current-voltage characteristics must first be clarified. Next, variation between n-type and p-type devices, lifetime, and temperature characteristics must be evaluated, followed by demonstrations of circuit operation using ring oscillators and SRAM. Beyond that lie standard cell PPA, circuit density including interconnects, wafer yield, design kits, and customer chips.
The 500,000 on-off ratio represents a figure that, within this sequence of evaluation stages, still sits at the point of confirming device characteristics.
Miniaturization Is Possible with DUV, But Process Steps Increase
Multiple patterning is a representative technique for forming fine patterns using DUV. Densely packed shapes that cannot be separated in a single exposure are divided into multiple parts, with exposure and processing repeated to form a single layer. This enables finer patterns, but the process becomes longer compared to EUV, which can form the same pattern in a single exposure.
In its 2025 annual report, ASML explained that DUV multiple patterning increases not only the number of exposures but also deposition and etching steps. According to the imec.netzero model cited by the company, EUV single patterning requires approximately 20% fewer process steps per wafer compared to DUV multiple patterning.
However, this 20% figure comes from a generalized environmental assessment model comparison, not a specific number representing the process steps, manufacturing costs, or yield of the Institute of Microelectronics.
Each additional process step requires additional masks, equipment operating time, materials, and inspection. Alignment errors from previous steps also accumulate. The technical possibility of forming a single layer and the economic question of applying that process across many layers while maintaining sufficient yield at acceptable cost are separate matters.
On its public webpage, the Institute of Microelectronics states that it researches optical proximity correction for both DUV and EUV, source-mask co-optimization, double patterning, and inverse lithography, targeting nodes from 45nm to 3nm.
The research scope includes not only GAA devices but also computational lithography technologies aimed at extending DUV's limits. However, the fact that "3nm" is listed as a research target does not itself mean that a specific 3nm GAA process has been completed and reached mass-production readiness.
What Circuit and Manufacturing Data Will Determine Going Forward
To evaluate the September 2026 report as a major manufacturing technology advance, what's needed first is a paper or official announcement corresponding to this specific result. If gate length, operating voltage, measurement temperature, absolute on-current and off-current values, and the number of devices evaluated are disclosed, the 500,000 ratio could be compared against other devices. Data on device-to-device variation and long-term reliability for both n-type and p-type devices would also be necessary.
At the circuit level, ring oscillator frequency and power consumption, SRAM read/write margins, and standard cell PPA would become important.
On the manufacturing side, questions include which layers were formed using DUV, how many masks were used, and what minimum pitch and overlay accuracy were achieved. Furthermore, if wafer diameter, defect density, yield including interconnect processes, design kits, and customer circuits are disclosed, comparison with commercial nodes would become possible.
In an environment without access to EUV, research combining GAA's three-dimensional structure with computational lithography has clear significance. If circuit and manufacturing data are disclosed going forward, it could further push the boundaries of what advanced logic using DUV can achieve.
What will determine that evaluation is neither the label "3nm" nor a single ratio of 500,000. It is power, performance, and area measured under identical conditions, together with wafer yield that accounts for the interconnect process as well.