External analysis has confirmed that Chinese DRAM maker ChangXin Memory Technologies (CXMT) has introduced High-k Metal Gate (HKMG) technology into its fourth-generation G4 process and LPDDR5X products. ZDNet Korea reported the finding on August 27, 2026, citing results presented at a TechInsights memory industry webinar. CXMT had already been mass-producing LPDDR5X, but had not disclosed the gate material used in its transistors. What has now come to light is not a product specification, but a technical assessment: CXMT has successfully integrated into mass production a process module that the three leading memory makers have long used to shrink their process nodes.
However, what can be confirmed from public information stops at the adoption of HKMG itself. Whether the high-k dielectric in the commercial product is hafnium dioxide (HfO2), which transistors the HKMG is applied to, and by how many percentage points it improves performance all remain unclear. Nor is HKMG an automatic ticket to the 1a generation for CXMT. Whether the company can advance from G4 to the G5 node currently under development hinges less on its ability to select a material and more on whether it can combine that material with multi-patterning and thermal processing steps to reliably produce good dies.
What the physical teardown actually confirmed
In April 2025, TechInsights published a report combining scanning electron microscopy (SEM), transmission electron microscopy (TEM), and materials analysis on CXMT's G4 16Gb DDR5 die, taken from a module manufactured by Powev. The analysis covered both the memory array and peripheral circuit structures. The firm then confirmed a G4 die in a commercially available DDR5-6000 UDIMM in August 2026, assessing that CXMT trails the three leading makers by roughly three years.
What was newly confirmed at the August 27 webinar was the presence of HKMG. According to ZDNet Korea, TechInsights classified G4 as a 16nm-class node and stated that HKMG had been "successfully introduced" into that process and into LPDDR5X. The next-generation G5, said to be under development as a 15nm-class node, was assessed as roughly two generations behind the leaders.
This kind of confirmation carries a strength that official corporate announcements lack: it is based on physically disassembling the product and observing its cross-sections and elemental composition. That said, the detailed report and webinar materials have not been made public. The elemental composition and thickness of the high-k film, the type of gate metal used, and the scope of its application cannot be traced from publicly available articles.
Any claim that CXMT has "replaced silicon with hafnium" goes beyond what has actually been verified. Multiple hafnium-based materials do appear in CXMT's patents, so such a material is a plausible candidate. But a list of materials named in a patent is not the same evidence as a material identified in an actual, commercially sold G4 die.
What's being replaced isn't the cell capacitor
A single bit of DRAM consists of a capacitor that stores charge and an access transistor that controls the flow of that charge in and out. Outside the array sit the peripheral CMOS circuits that drive the sense amplifiers, I/O circuitry, and power circuits. Conflating talk of HKMG with the high-k dielectric used in cell capacitors leads to a misreading of exactly what has advanced.
When SK hynix introduced HKMG into LPDDR5X in 2022, it explicitly stated that the target was the peripheral circuit transistors. As cells shrink, peripheral circuits must shrink too, and they need to deliver sufficient drive strength at lower voltages. If the conventional SiON gate dielectric is made too thin, electrons pass through the film via quantum tunneling, degrading standby power consumption and reliability.
A high-k film allows a physically thicker layer to be used while maintaining the same electrical thinness. This lets the gate exert strong control over the channel while reducing tunneling leakage. SK hynix has described the dielectric constant of the high-k material it adopted as roughly five times that of conventional SiON.
When a high-k film is paired with a polysilicon electrode, resistance and depletion effects interfere with device operation. That's why the electrode is also switched to metal, with its work function tuned to align the threshold voltages of NMOS and PMOS transistors. The "MG" in HKMG is not an afterthought—fully exploiting a high-k film in a low-voltage, high-speed transistor requires a metal gate as well.
Regarding CXMT, published reporting does not specify that the application target is the peripheral circuitry. While TechInsights' analysis covered both the array and peripheral structures, which cross-section the HKMG was identified from is not disclosed outside the paid report. It therefore cannot be concluded that CXMT's cell access transistors in G4 have also shifted to HKMG.
What CXMT's patents reveal about the thin-film, thick-film balancing act
CXMT's patent CN116344602A, filed in December 2021, explains that thinning SiO2 in DRAM manufacturing produces non-negligible gate leakage, necessitating the introduction of a high-k film. Candidate materials listed include hafnium silicate, hafnium silicon oxynitride, and hafnium tantalum oxide, with hafnium titanium oxide and hafnium zirconium oxide also among the options. This patent, registered in China in January 2026, serves as primary-source evidence that CXMT has been researching hafnium-based gate stacks.
What this patent is really trying to solve isn't a matter of naming a material—it's an interfacial reaction. When oxygen migrates between the hafnium oxide and the silicon, oxygen vacancies form in the high-k film. The movement of these vacancies and electrons can shift the effective work function of the metal gate, potentially degrading the transistor's electrical characteristics. CXMT proposed a structure that inserts a barrier layer containing the same metal element as the high-k film to suppress this oxygen migration.
Another patent, CN117690785A, filed in August 2022, paints an even more concrete picture of the difficulties of mass-production integration. DRAM peripheral circuits contain a mix of thin-oxide devices that operate fast at low voltage and thick-oxide devices that handle higher voltages. According to the patent, if the high-k film is left in place over the thicker dielectric layer, dipole diffusion is impeded, preventing the metal gate from adequately adjusting the threshold voltage.
CXMT's proposed solution is to retain the high-k film on the thin-oxide side while selectively removing it on the thick-oxide side. The same mask is used for both positive and negative development, which also helps limit the increase in process steps and cost. Mass-producing HKMG isn't a single step of "depositing a new material"—it only makes it into a product once multiple operating voltages and interfacial reactions are made to work together while keeping the number of masking steps under control.
Of course, patents indicate a direction for R&D; they do not prove a commercial product's actual recipe. Which of the materials listed in CN116344602A was actually adopted for G4, and whether the selective removal process from CN117690785A was used on the same die, remain undisclosed. Only if TechInsights' materials analysis is made public could these two pieces of information finally be connected.
The distance from Samsung in 2021 and SK hynix in 2022
Samsung Electronics announced a DDR5 module using HKMG in March 2021, stating that it reduced power consumption by 13% compared to its previous process. Because this was announced alongside stacking technology supporting higher capacities, the 13% figure reflects Samsung's own product conditions, including HKMG, and cannot be directly applied to CXMT.
SK hynix adopted HKMG for its 1a-generation LPDDR5X in 2022, stating that it had improved both speed and power consumption over the previous generation. The company evaluated defects and stability in pilot products before moving to mass production, adjusting its process to avoid adverse effects on the connection between the peripheral circuitry and the cell array.
| Company | Time HKMG announced/confirmed | Target | Publicly disclosed achievement |
|---|---|---|---|
| Samsung Electronics | 2021 | DDR5 | 13% reduction in power consumption vs. previous process |
| SK hynix | 2022 | 1a-generation LPDDR5X | Improved speed and power consumption vs. previous generation |
| CXMT | Externally confirmed August 2026 | G4, LPDDR5X | TechInsights confirmed HKMG adoption; improvement rate undisclosed |
This timeline suggests that CXMT's achievement is not a world-first materials innovation, but rather a milestone in which the company has moved a process module—one the leading players commercialized three to five years ago—into its own mass-production flow. According to CXMT's official announcements, its 8,533Mbps and 9,600Mbps products entered mass production in May 2025, while its 10,667Mbps product was still at the customer-sampling stage as of October of that year. The confirmation of HKMG offers a glimpse of part of the manufacturing technology underpinning this low-voltage, high-speed operation.
However, the same technology name does not mean the same performance. Differences in film quality and interface defects change leakage current. Transistor dimensions and circuit design also affect speed. How close CXMT has actually come to Samsung or SK hynix cannot be judged without power, speed, and area figures measured under the same conditions.
The good-bit yield that will decide G5's fate
The prospectus CXMT submitted to the Shanghai Stock Exchange states that on its fourth-generation platform, it will continue increasing capacity and performance for LPDDR4X, DDR5, and LPDDR5X, while its fifth generation remains at the research stage. The stated goal for G5 is to boost memory density and array performance through "further-optimized multi-patterning." CXMT itself has not disclosed the nanometer-scale naming convention that would map G4 to 1z or G5 to 1a.
What HKMG primarily helps with is shrinking peripheral transistors while keeping them operating at low voltage. Advancing the overall DRAM generation still requires reducing cell area, maintaining capacitor capacitance, and suppressing wiring and contact resistance. If multi-patterning steps increase for G5, the number of exposure, deposition, and etching steps rises accordingly, and misalignment and defects accumulate. Even if the design reaches 15nm, manufacturing cost per bit won't fall if the yield rate is low.
Equipment procurement also affects the entire process. The export controls on China announced by the U.S. Commerce Department's Bureau of Industry and Security (BIS) in December 2024 covered not only certain lithography equipment but also deposition and etching tools, with metrology, inspection, and cleaning equipment also falling within the scope of regulation. Because it is not publicly known which equipment CXMT's G5 will use, the specific impact cannot be determined. Even so, securing HKMG materials domestically does not translate into an absence of constraints on process miniaturization.
TechInsights classifies G4 as a 16nm-class node and the G5 under development as 15nm-class, estimating the gap with leading players at roughly two generations. Even if the numerical difference is just 1nm, the increase in process steps and the ramp-up of yield are not linear. HKMG has become one element enabling progress toward G5. What's needed next is not simply for G5 prototype dies to function, but for the company to move to mass production while maintaining density and good-die yield.
As for CXMT's production capacity, research firm Counterpoint Research estimates it at 320,000 wafers per month as of 2026, rising to 420,000 wafers per month in 2027. The firm also sees CXMT as having a plan to double current capacity by 2030. However, a figure suggesting CXMT will reach 800,000 wafers per month by 2031 cannot be confirmed as a plan the company has officially announced.
Increasing wafer input volume does not automatically raise the competitiveness of G4 or G5. The number of good-bit units actually shipped depends on the combination of dies obtained per wafer, yield rate, and capacity per die. Furthermore, the revenue and profit generated by a single wafer differ across LPDDR, general-purpose DDR, and HBM. Comparing monthly wafer output alone with Micron or Samsung cannot simultaneously measure technological gap and supply capacity.
The economic significance of adopting HKMG lies not only in suppressing G4's leakage current, but in whether CXMT can shrink the die while preserving peripheral circuit performance, thereby increasing the number of good bits obtained per wafer. Yet CXMT has not disclosed G4's die area, bit/mm2 density, numerical yield rate, or cost per bit. These figures would measure the pressure CXMT is placing on the three leading makers far more precisely than the projected rise from 320,000 to 420,000 wafers per month.
Whether G5 achieves competitiveness comparable to the 1a generation can be judged once external analysis verifies HKMG's material composition and scope of application, once the 10,667Mbps LPDDR5X moves from customer sampling to mass production, and once G5's die area and yield rate are disclosed. Only when those conditions are met will CXMT progress from being a manufacturer that simply increases its wafer count to one that translates process miniaturization into improvements in good-bit yield and manufacturing cost.