Dongfang Suanxin, a Chinese AI chip startup, said at ICChina (the integrated circuit exhibition held as part of the China International Industry Fair) in Shanghai on October 12–16, 2026, that a cluster of 128 DF1000 chips is running stably. The DF1000 is a 14nm AI chip that does not use HBM (high-bandwidth memory). Xu Ziming, the company's marketing director, told Jiemian News that its first large-scale training cluster has entered the stage of delivery to customers. Reports that read close to company announcements also describe 72 hours of continuous training and the porting of a model of roughly 130 billion parameters to the DF1000 in seven days. However, stable operation of a 128-card configuration was already claimed at the July 13 announcement, and basic specifications such as memory capacity and power consumption remain undisclosed. Xu himself acknowledged that production capacity for the first-generation product is limited, so this announcement alone is not enough to fully assess the DF1000's practicality as a training AI chip.
The 128-card cluster was announced in July; October added 72 hours of continuous training and a model-porting result
When Dongfang Suanxin announced the DF1000 on July 13, it said it had finished validating prototype chips and that all functions ran stably on a large 128-card cluster (according to Guancha.cn). Stable operation of 128 cards is therefore not a result revealed for the first time in October. What is new is information about actual operation: the types of models supported, the duration of continuous training, and the status of delivery to customers.
Xu Ziming disclosed three main developments to Jiemian News. First, mainstream large models can be migrated to train on the DF1000 within seven days. Second, the first large-scale training cluster has entered the customer delivery stage. Third, the company plans to deliver a cluster on the scale of 1,000 cards by the end of 2026. The customer's name, the specific number of units delivered, and how the system is performing in the customer's environment were not disclosed.
More detail on operating results came from an article by Zhidx (republished by Jiemian News as an advertisement) and one by Kuai Keji. Both rely mainly on the company's own account and read as promotional, so they cannot be treated as independent verification. According to the two articles, the 128-card cluster trained for 72 hours without interruption, and training accuracy met the specified standard. It is also said to have supported training of multiple large models, including Llama2-70B and a model the company calls JYXC-130B. For a model of roughly 130 billion parameters that the company calls Step 130B, it says it completed adaptation to the DF1000 in seven days. Kuai Keji adds that the period from the start of development until the cluster became capable of training was 24 months.
One caveat: the "seven days" is not the time taken to finish training a model. The figure refers to the time spent on software porting and tuning to make an existing model trainable on the DF1000. What Xu Ziming described to Jiemian News was a general development capability, that mainstream models can be adapted within seven days, and he did not mention Step 130B by name. Model-porting time and training time are different metrics and should not be confused.
Other Chinese AI chip companies also promoted large clusters at the expo. MetaX showed its 64-card Xijing S600, Enflame showed the Yunsui ESL64-O, and Iluvatar CoreX exhibited a rack-scale system with 144 GPUs. Because the building blocks differ, the scales cannot be compared directly, but the displays suggest that Chinese AI chip companies are now competing not only on the performance of individual chips but also on the operating capability of whole systems that combine many accelerators.
What 72 hours of continuous training confirms, and the memory capacity and power consumption still undisclosed
A 72-hour continuous training run tests whether a cluster can operate for a long time without stopping. In large-model training, many accelerators exchange results frequently as they work, so the failure of a single card or communication link can bring down the whole system. In that case training must resume from a saved checkpoint, although some systems have mechanisms to route around faults and keep processing. The company's explanation does not say whether the DF1000 cluster has such fault-tolerance features. Even so, long continuous operation has value for exposing failures and thermal-management problems that short benchmarks can miss.
On the other hand, a record of running 72 hours without stopping says nothing about how high the training performance is. Training throughput (how much learning proceeds per hour), time to reach a target accuracy, and the performance gain as cards are added each require separate measurement. System stability and computing performance are different evaluation criteria, and the operating results released in October do not show training speed itself. Comparing the information released in July and October gives the following:
| Item | At the July announcement | October explanation | Disclosure status |
|---|---|---|---|
| Continuous operation record | Said all functions ran stably on 128 cards | 72 hours of continuous training without interruption (company-side article) | Continuous training result disclosed |
| Model porting/tuning time | Not disclosed | Mainstream models within 7 days; Step 130B in 7 days (company's explanation) | A different metric from training time |
| Training time to the same accuracy | Not disclosed | Not disclosed | Undisclosed |
| Performance gain when adding cards | Not disclosed | Not disclosed | Undisclosed |
| Memory capacity | Not disclosed | Not disclosed | Undisclosed |
| Power consumption | Not disclosed | Only a statement that specification tests were completed, with no figures | Undisclosed |
| Customer name and deployment count | Not disclosed | First cluster at the customer delivery stage (no customer named) | Undisclosed |
| Foundry and DRAM supplier | Not disclosed | Not disclosed | Undisclosed |
The October announcement newly showed 72 hours of continuous training, seven days of model porting and tuning, and the first large-scale cluster entering the delivery stage. However, memory capacity, power consumption, customer names, training throughput and other details are still undisclosed. The Zhidx article says all specification tests covering accelerator-card computing performance, memory bandwidth, communication bandwidth, power consumption and temperature have been completed, but it gives no concrete measurement results. It also claims computing efficiency reached 85% or more, but the measurement conditions are unknown and there is no independent verification, so this is insufficient as a basis for evaluating performance.
This comparison is based on published reports and company communications, and it cannot be ruled out that detailed specifications appear in non-public materials provided to customers. Two of the three reports from October rely on the company's own account, so there are limits to their independence. As for manufacturing, Dongfang Suanxin says the entire process, from chip design through 14nm wafer fabrication, 3D packaging and testing, is completed within China's domestic supply chain. However, the foundry and DRAM supplier have not been named, making it difficult for outsiders to verify supply-chain details.
DF1000 secures about 2.5 times the H200's memory bandwidth per unit of compute
The DF1000's published specifications are BF16 (a 16-bit number format widely used in AI model training) compute performance of 520 TFLOPS and memory bandwidth of 6.4TB/s. Dividing compute by memory bandwidth gives about 81 FLOP/Byte, meaning that at peak performance about 81 floating-point operations can be executed while one byte of data is read from memory. For comparison, NVIDIA's published BF16 performance for both the H200 SXM and H100 SXM is 1,979 TFLOPS under sparsity. Taking the non-sparse figure as half of that, 989.5 TFLOPS, and dividing by their memory bandwidths of 4.8TB/s and 3.35TB/s respectively gives about 206 FLOP/Byte for the H200 SXM and about 295 FLOP/Byte for the H100 SXM.
In this comparison, the DF1000 comes to about 81 FLOP/Byte against about 206 for the H200 SXM and about 295 for the H100 SXM. In other words, the DF1000 is designed with relatively large memory bandwidth for its peak compute. Put the other way, in memory bandwidth available per operation, the DF1000 equals about 2.5 times the H200 SXM and about 3.6 times the H100 SXM. The Zhidx article likewise puts the ratio for mainstream GPUs at 150–300 FLOP/Byte and says the DF1000 secures 2 to 3.6 times the GPUs' memory bandwidth per operation. The upper figure of 3.6 times can be reproduced from the H100 SXM's published values, but which GPU the lower figure of 2 times refers to is not stated.
The smaller the compute-to-bandwidth ratio, the easier it is, relatively speaking, to supply the data transfer needed to sustain peak compute. Large-model computation requires continuously sending huge amounts of weights and intermediate data from memory to the compute units. If data supply cannot keep up, the compute units sit idle and cannot fully deliver their catalog performance. This condition, in which memory bandwidth limits performance, is called being "memory-bound," and the DF1000 appears to be trying to ease the problem by providing thicker memory bandwidth relative to compute.
However, whether memory limits actually occur depends on model structure, batch size, software optimization and other factors. Even with relatively large memory bandwidth, training is not necessarily faster. Judging training performance requires training throughput and time-to-target-accuracy measured under equivalent conditions, but Dongfang Suanxin again did not release these. Important information is still missing for confirming whether the DF1000's design features translate into actual performance gains.
According to the company-side article, the DF1000 secures high memory bandwidth through "hybrid bonding," which directly bonds a DRAM wafer and a logic wafer. This method shrinks the conventional connection pitch of tens of micrometers to below one micrometer and raises connection density by several orders of magnitude. The decision not to use HBM also reflects constraints on procuring advanced memory. The US Commerce Department's Bureau of Industry and Security (BIS) added HBM to export controls in a December 2024 rule, applying the restrictions to US-made HBM as well as foreign-made HBM covered by the foreign direct product rule.
Still, the comparison between the DF1000 and NVIDIA GPUs is based solely on the ratio of published peak performance to memory bandwidth. It does not mean the DF1000 can train models faster than the H200. Dongfang Suanxin also has not said whether the 520 TFLOPS figure is for dense matrix operations without sparsity. If it were a sparse figure, the ratio based on dense performance would be even lower, though the assessment that the design emphasizes memory bandwidth would not change. In addition, this comparison does not include memory capacity or power consumption, and it does not evaluate overall system efficiency.
First-generation capacity is limited; second-generation deliveries planned for the second half of 2027
Xu Ziming told Jiemian News that the production capacity secured for the first-generation product is relatively limited, and the scale of current deliveries is constrained accordingly. Meanwhile, the company expects to begin "tape-in" of the second-generation chip, meaning the start of wafer input into the production line, at the end of 2026, with deliveries starting in the second half of 2027. At the July announcement, the company had said through Vice President Guo Wei that it would launch the DF2000 in the fourth quarter of 2026 with twice the DF1000's compute performance. It also indicated a plan to launch the DF3000 in the fourth quarter of 2027, doubling performance once more.
The October explanation does not mention the second-generation product's name, but given the development sequence it presumably refers to the DF2000. However, the "launch" used in July and the "tape-in" used in October do not necessarily mean the same stage. The former refers to market release and the latter to the start of the manufacturing process, so the two are not necessarily contradictory. Even so, the newly stated customer delivery start is the second half of 2027, and that timing is what matters in judging the mass-production and supply schedule.
| Timing | Event | Category |
|---|---|---|
| May 20, 2024 | Shanghai Dongfang Suanxin Technology Co., Ltd. established | Actual |
| April 2026 | A+ round completed; post-investment valuation reported at 12.275 billion yuan | Actual (reported) |
| July 13, 2026 | DF1000 announced in Shanghai | Actual |
| July 13, 2026 | Stable operation of all functions on a 128-card cluster announced | Company claim |
| October 12–16, 2026 | At ICChina, explained that the first cluster entered the customer delivery stage and a 1,000-card-class cluster delivery is planned by year-end | Company explanation |
| End of 2026 | Delivery of a 1,000-card-class cluster | Plan |
| End of 2026 | Start of wafer input for the second-generation chip | Plan |
| Second half of 2027 | Start of second-generation chip deliveries | Expected |
| Q4 2027 | Launch of the DF3000 | Plan (as of July) |
In about two and a half years since its founding in May 2024, Dongfang Suanxin has announced the DF1000, reported stable operation of a 128-card cluster, and reached the stage of delivering its first large-scale cluster to a customer. Second-generation deliveries, however, are expected only in the second half of 2027. The company is headquartered in Zhangjiang, Shanghai, and has more than 500 employees. Chairman and CEO Wei Shaojun is a professor at Tsinghua University and also serves as a vice chairman of the China Semiconductor Industry Association. According to Jiemian News, the A+ round completed in April 2026 valued the company at 12.275 billion yuan post-investment, equivalent to about 290.8 billion yen or about $1.84 billion at the October 30, 2026 exchange rate (1 yuan = 23.693201 yen, $0.150125). The company plans to begin a Series B fundraising in the fourth quarter of 2026.
The plan to deliver a 1,000-card-class cluster by year-end shows that Dongfang Suanxin aims to expand its supply scale. But since an executive himself acknowledges that first-generation production capacity is limited, the company appears at this stage to be validating cluster operation in real customer environments rather than supplying large volumes. The company has not given a specific explanation of why capacity is constrained.
The 3D stacking technology the DF1000 adopts also has manufacturing challenges to overcome. At a forum held alongside ICChina, Guo Wei pointed out that stacking chips can shorten interconnect distances but makes yield and heat dissipation harder to manage. He also said the industry as a whole lacks simulation tools that can predict yield and thermal characteristics after 3D integration at the design stage. Pan Yu, vice president of Hygon Information, likewise said the practicality of 3D integration depends on whether it meets requirements for yield, stability, sustained performance and cost, and that for customers more stacked layers are not necessarily better.
Whether the DF1000 can proceed to full commercial supply will be judged by future manufacturing and delivery results and by the disclosure of performance information. The first focus is whether the company can deliver the planned 1,000-card-class cluster by the end of 2026, and whether it can start second-generation wafer input around the same time and lead to deliveries in the second half of 2027. Concrete figures are also needed for memory capacity, power consumption and training throughput, none of which have been disclosed since the July announcement. Once that information is available, it will be possible to judge more objectively whether the DF1000's approach of stacking DRAM directly on logic chips can become a practical choice of training infrastructure for Chinese AI developers facing constraints on HBM procurement.