The POWERlab at the Swiss Federal Institute of Technology in Lausanne (EPFL) has built a normally-off transistor using gallium nitride on silicon (GaN-on-Si) that blocks 3.4 kV. A paper published in Nature Electronics on August 28, 2026, reports that a separate normally-on device built on the same polarization super-junction platform showed less than a 15% increase in dynamic on-resistance even after 3 kV off-state stress. The work demonstrates both high static blocking voltage and the dynamic characteristic of returning to low resistance after switching, across two separate prototype devices.

3.4 kV is not the highest voltage ever achieved by a GaN transistor overall—prior research on sapphire substrates has blocked 10 kV. What's new here is the use of inexpensive silicon substrates, achieving charge balance in the drift region without intentional impurity doping, and eliminating field plates used for electric field relaxation. That said, the device as a whole is not entirely dopant-free: local contacts to the two-dimensional hole gas use Mg-doped p-GaN. The 3.4 kV figure for the normally-off device and the low dynamic resistance increase for the normally-on device need to be evaluated as separate achievements.

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Why 3.4 kV Matters Even Though It's Not a Record

GaN research records, commercial GaN products, and 3.3 kV-class silicon carbide (SiC) products prove different things even when their voltage figures are similar. A research device's measured "blocked up to this voltage" is not the same as a commercial product's guaranteed rated voltage. Nor can it be placed on the same level as a complete product module, which includes current rating, packaging, and certification testing.

Device Substrate/Structure Voltage On-Resistance After High Voltage Maturity Stage
EPFL iPSJ normally-off (2026) GaN-on-Si, dopant-free polarization super-junction drift region 3.4 kV blocked Paper's 3 kV dynamic test is for a separate normally-on device Peer-reviewed research device
EPFL iPSJ normally-on (2026) GaN-on-Si, dopant-free polarization super-junction drift region 3.5 kV blocked Increase under 15% at 3 kV Peer-reviewed research device
GaN super-heterojunction FET (2024) GaN-on-sapphire, two-channel 10 kV blocked 123% increase at 3 kV Peer-reviewed research device
EPFL prior normally-off device (2025) GaN-on-Si, junction tri-gate 2.7 kV blocked Not shown in comparison materials Peer-reviewed research device
Infineon CoolGaN product line GaN transistors 60–700V rated Specified per product Commercial product
Innoscience high-voltage GaN line Normally-off GaN 650–1200V rated Specified per product Commercial product
Infineon CoolSiC XHP 2 SiC half-bridge module 3.3 kV rated Absolute on-resistance 1.9–3.8 mΩ Commercial product, 500–1000A

EPFL's 3.4 kV is not the overall breakdown voltage record for GaN. What matters this time is that on a GaN-on-Si iPSJ platform that avoids intentional doping for charge matching in the drift region, a normally-off device blocked 3.4 kV, and a separate normally-on device kept the dynamic on-resistance increase under 15% after 3 kV stress. These two figures do not come from the same transistor.

The prior 10 kV device saw its on-resistance increase by 123% after a 3 kV dynamic test, with a specific on-resistance of 73.5 mΩ·cm². In this study, the normally-on device that kept the increase under 15% after 3 kV had a specific on-resistance of 6.3 mΩ·cm². The normally-off device showed 11.1 mΩ·cm² and demonstrated a static blocking voltage of up to 3.4 kV. While no single device satisfied every condition, the work advances the design principle of returning to low loss immediately after switching high voltage—separate from achieving maximum blocking voltage.

The distance to commercial products should not be misjudged either. EPFL's press materials describe the achievement as more than five times the voltage of commercial 600–650V-class GaN, but as of August 31, 2026, Infineon offers products up to 700V and Innoscience up to 1200V. Meanwhile, in the 3.3 kV class, SiC modules already exist as products handling 500–1000A. EPFL's prototype has pushed GaN-on-Si into the same nominal voltage range, but it has not matched SiC as a current-carrying product.

Breaking Up Electric Field Concentration with Two Thin Charge Layers

Lateral GaN transistors use the two-dimensional electron gas that forms at the AlGaN/GaN interface as the current path. Electrons gather at high density in this thin layer, enabling fast, low-resistance operation. However, in the off state, fixed charges remaining at the surface or in the buffer cause electric field concentration at the edges of gates and electrodes. Localized fields reach the material's limit before the rest of the drift region is fully utilized, causing the device to break down prematurely.

In high-voltage silicon MOSFETs, super-junctions—alternating n-type and p-type pillars—have long addressed this imbalance. By precisely balancing positive and negative impurity charges and depleting the drift region in the off state, the electric field spreads across a wider area. However, GaN struggles to form high-quality p-type regions, and even slight variations in doping concentration or temperature can easily disrupt this charge balance.

POWERlab's dopant-free polarization super-junction (iPSJ) does not rely on impurity concentration to determine drift-region charge. Instead, it uses the spontaneous and piezoelectric polarization inherent to III-nitride materials. By placing a thick, undoped GaN cap of about 160 nm over the two-dimensional electron gas at the AlGaN/GaN interface, an equal number of two-dimensional holes forms at the opposite GaN/AlGaN interface. When electrons and holes are simultaneously extracted in the off state, the drift region becomes nearly charge-neutral, flattening the peak of the electric field.

The two-dimensional hole gas is not the main conduction path. Because hole mobility is lower than electron mobility, its contribution to on-state current is small. Here, holes function as a "movable counterweight" that balances the electron layer's charge. Unlike fixed impurity charges, they can be expelled the moment the switch turns off.

That exit route is an ohmic contact to the two-dimensional hole gas, formed by locally growing 50 nm of Mg-doped p-GaN. During the transition to the off state, holes are rapidly withdrawn to maintain balance with electrons; when switching back on, holes are injected to compensate for trapped electrons. In the paper, when this contact was left floating, the dynamic blocking voltage dropped to 500V and on-resistance also increased. The term "dopant-free" refers to charge matching in the drift region, not to the entire device including this contact. Both the design that creates equal numbers of charges and the contact that moves those charges in and out were necessary.

The thick GaN cap serves another purpose. It acts as an epitaxial protective layer that keeps conducting electrons away from surface trap states, making electrons less likely to become stranded at the surface after high voltage is switched off. This allowed the iPSJ to align both electric field distribution and dynamic on-resistance without relying on surface passivation layers or field plates.

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What It Means to Recover On-Resistance After 3 kV

Diode measurements most directly reflect the effect of charge balance. A Schottky barrier diode with a 25 µm super-junction region recorded a forward turn-on voltage of 0.75V and a specific on-resistance of 4.7 mΩ·cm² at room temperature. In reverse, it blocked 3.6 kV with a current limit of 100 µA/mm, and did not break down even at 3.9 kV, where current reached 0.95 mA/mm. Leakage current remained nearly flat up to 3.1 kV, beyond which GaN-on-Si buffer leakage dominated.

Reproducibility was also examined. When the same device was swept 17 consecutive times up to 3.3 kV, variation in the leakage current curve stayed within a 20% standard deviation. Blocking voltage exceeded 3.3 kV across 25–125°C. The authors describe the temperature dependence and reproducibility as resembling "avalanche-like breakdown," though this does not constitute quantitative proof of avalanche capability.

In dynamic testing, a high reverse voltage was applied to the device for 1 second, followed by turning it on for just 1 ms at 3V. Averaging resistance over 0.75–1 ms, the charge-balanced iPSJ showed only a small increase up to the equipment's 3 kV limit, at both 25°C and 125°C. In contrast, an unprotected reference diode showed dynamic on-resistance exceeding 50 times its static value, with a dynamic blocking voltage below 200V. This is a difference invisible from static blocking voltage curves alone.

For transistors, the normally-on device recorded a threshold voltage of -7V, specific on-resistance of 6.3 mΩ·cm², and blocking voltage of 3.5 kV. The normally-off device, meanwhile, showed a threshold voltage of 0.67V, specific on-resistance of 11.1 mΩ·cm², and blocking voltage of 3.4 kV. Both achieved on/off current ratios exceeding 100,000.

The normally-on device's dynamic on-resistance was confirmed up to 650V in continuous on-wafer pulse measurements, and up to 3 kV using single-pulse equipment. In the single-pulse test at 3 kV, off-state voltage was applied for 10 ms, followed by a 200 µs wait—to avoid damage or measurement error from cable discharge—before switching on, with resistance measured 40–140 µs after turn-on. The device with ohmic contact to the two-dimensional hole gas showed less than a 15% increase even after 3 kV. A reference MOSHEMT showed more than a fourfold increase from just 50V off-state stress. However, 3.4 kV is the static blocking voltage obtained from a separate normally-off device, not the result of continuously operating a packaged device at 3.4 kV.

Four Tests That Will Determine Commercialization

First is current and area. The paper reports specific on-resistance but does not indicate rated current for a product, chip area, or thermal resistance. While lateral GaN-on-Si makes it easy to integrate multiple power devices on a single wafer, scaling up current introduces new constraints in wiring, heat dissipation, and current crowding.

Second is hard switching in actual circuits. The diode's dynamic test transitioned from a 1-second off state to just 1 ms on at 3V. Meanwhile, the transistor's single-pulse test at 3 kV involved 10 ms of off-state stress, a 200 µs wait, and resistance measured 40–140 µs after turn-on. Neither test replicates the repeated hard switching of actual circuits, and neither measures switching frequency, conversion efficiency, or turn-on/turn-off switching losses. Whether the normally-off device's 0.67V threshold voltage provides sufficient gate margin in noisy real-world implementations also requires verification.

Third is long-term reliability. The 17 sweep cycles and 125°C measurements support reproducibility and thermal stability, but remain far from product certification, which includes short-circuit withstand capability, power cycling, extended high-temperature/high-humidity bias testing, and cosmic-ray-induced failure. The avalanche-like breakdown behavior would also need measured energy absorption capacity and repeat cycle counts before it could inform circuit design.

Fourth is simultaneously managing lower resistance and mass-production variability. POWERlab's 2.7 kV normally-off multi-channel device, reported in 2025, achieved a specific on-resistance of 2.8 mΩ·cm². The current 3.4 kV device shows 11.1 mΩ·cm². The research team has indicated plans to combine multi-channel structures with iPSJ as a next step, increasing the number of current paths. Whether resistance can be lowered while maintaining uniform cap thickness (~160 nm), interface charge, and hole contacts across an entire wafer will be the manufacturing test.

Whether GaN-on-Si enters the territory of 3.3 kV-class SiC will be determined not by the maximum blocking voltage, but by whether the under-15% resistance increase after 3 kV—demonstrated in the normally-on device—can be reproduced in normally-off devices, high-current chips, and packaged products. If multi-channel structures, circuit demonstrations, and long-term certification all come together in the same device, the vision of integrating high-voltage switches and drive circuits on a silicon substrate becomes a realistic option.