On July 22, 2026, Hitachi, Ltd. announced that a NEDO project jointly proposed with Intel's Japan subsidiary had been selected as a prospective contractor for research and development aimed at scaling up next-generation quantum computers. The project is scheduled to run until March 2029, and Hitachi will also conduct joint research with the National Institute of Advanced Industrial Science and Technology (AIST).
As of March 2026, Hitachi had already announced plans to aim for a silicon quantum device with 100 qubits by fiscal year 2028 and one with 1,000 qubits by fiscal year 2030. What is new this time is the addition of a quantum device manufacturing process based on Intel's 18A process technology and a process design kit (PDK) for qubit chips. The plan is to move from research on precisely controlling single qubits toward reflecting manufacturing conditions in the design process, restructuring cryogenic packaging and external access into a single unified workflow.
Intel 18A and the Qubit PDK
In research published by Hitachi and others in 2026, a single spin qubit on natural silicon achieved an improvement in single-qubit gate fidelity from 95% to 99.1±0.1%. This was accomplished by continuously applying phase-modulated microwaves to protect the quantum state from noise. However, the experiment targeted only a single qubit. Placing many elements on the same chip requires simultaneously addressing device-to-device performance variation, peripheral circuitry, wiring, and packaging.
The PDK announced this time brings manufacturing conditions into the research side's design process. A PDK compiles a semiconductor fab's manufacturing conditions and design rules into a design tool. Intel will develop a PDK for qubit chips to support Hitachi's design work, and Hitachi will determine chip structures based on actual manufacturing conditions. The announcement states that a quantum device manufacturing process based on Intel 18A will be applied, but it does not explain whether the individual transistor technologies used in the standard logic-oriented 18A process will be directly transferred to qubits as-is.
The design targets extend beyond qubits alone. With future error correction in mind, Hitachi will incorporate peripheral circuitry, and will also develop components that hold the chip at cryogenic temperatures as well as control circuitry to reduce the number of wiring connections. The plan is to first build a design and packaging foundation for chips carrying 100 or more qubits, and then use 3D packaging—connecting chips and components at narrow spacing—to address the increased wiring and packaging area that comes with scaling to the 1,000-qubit class.
Here, two distinct scaling efforts are being pursued: within the chip and across the system as a whole. What the PDK handles is the process of translating manufacturable structures into a chip design carrying 100 or more qubits. 3D packaging, meanwhile, connects that chip at high density under cryogenic conditions and suppresses the area occupied by control wiring. Even if the former succeeds, the latter problem remains, which is why Hitachi has separated design and packaging into distinct development items.
In 2023, Intel provided "Tunnel Falls," a 12-qubit research chip manufactured on 300mm wafers, to universities and national research institutions. This latest collaboration goes beyond the goal of expanding qubit counts past 100—it also establishes an environment in which Hitachi designs using Intel's manufacturing rules. That said, "industrial quality" is the name of a development item, and pass criteria such as yield or fidelity have not been disclosed. Nor is this an announcement of the start of mass production.
Four Stages from Fiscal Year 2027 to Fiscal Year 2030
The numbers listed in the roadmap do not all refer to the same sense of "qubit count." It is necessary to distinguish between the cloud release, the prototype machine carrying quantum error-correcting codes, and long-term fault-tolerant quantum computation.
| Timing | Announced Milestone | What It Does Not Yet Mean |
|---|---|---|
| By FY2027 | Release of a cloud experimental environment via G-QuAT | Release of a 100-qubit prototype; a completed commercial service |
| FY2028 | 100-qubit-class prototype implementing quantum error-correcting codes | 100 logical qubits; complete fault tolerance |
| March 2029 | Scheduled end of this NEDO project | Achievement of the 1,000-qubit goal |
| FY2030 | 1,000-qubit-class prototype implementing quantum error-correcting codes | Completion of a practical fault-tolerant quantum computer |
No qubit count is specified for the FY2027 cloud release. Nor does the announcement state that the FY2028 100-qubit prototype will be usable starting the previous year. Additionally, the FY2030 target of 1,000 qubits is placed at a point in time beyond the NEDO project, which is scheduled to end in March 2029. It is a milestone within a longer research plan that also includes the second phase of the JST Moonshot program, in which Hitachi is participating in parallel.
Hitachi explains that a fault-tolerant quantum computer—one that corrects errors caused by noise while performing computation—will require integration on the scale of a million qubits. The 100 and 1,000 qubit figures announced here represent two prototype stages on the way to that goal. The announcement does not indicate how many logical qubits would be obtained from scales of 100 or 1,000 physical qubits, nor what depth of logical circuit could be sustained after error correction.
What Will Be Released on the FY2027 Cloud
In March 2026, AIST's G-QuAT began providing external access to superconducting and neutral-atom quantum computers via the quantum-classical hybrid computing platform "ABCI-Q." This time, Hitachi and AIST plan to develop a cloud system supporting an experimental environment for qubit chips and control devices, and to release the silicon-based approach via G-QuAT. Hitachi describes this as a new initiative for G-QuAT.
Hitachi states that it will enable external researchers and engineers to use the experimental environment for qubit chips and control devices, thereby improving the efficiency of research and development. The plan is to create an environment in which a broad range of talent can participate, contributing to the formation of an open development ecosystem.
However, it is not specified whether the silicon quantum computer will be integrated into ABCI-Q or provided through a separate mechanism. Usage fees and eligible users have not been announced, and neither the regions of availability nor operating hours are known. What begins in FY2027 is the release of the experimental environment; Hitachi states that it will subsequently roll out services in stages.
Parallel Development: Superconducting Beyond 10,000 and Silicon
NEDO's g12-1 call received two proposals, and the list of prospective contractors features two different approaches side by side. One is Fujitsu's large-scale implementation for a superconducting machine exceeding 10,000 qubits; the other is the large-scale, high-reliability silicon quantum computer from Hitachi and Intel. Rather than narrowing down to a single device architecture, the national project for next-generation machines is running multiple different scaling paths in parallel.
Qubit count alone cannot be used to compare the progress of the two projects. Different architectures involve different physical qubit quality and connectivity, as well as different control methods. The number of physical qubits required for error correction also differs between them. NEDO's list indicates prospective contractors for development; it is not an evaluation declaring either side the winner in a performance competition. The allocation of project funding has also not been disclosed.
The first indicator for gauging progress on the Hitachi-Intel side will be the scale of experimental environment made available to whom in FY2027. Next will come the question of how far multi-qubit operations and quantum error-correcting codes can be run on the FY2028 100-qubit prototype while suppressing manufacturing variation and wiring complexity. The results of placing the PDK, 3D packaging, and cloud access on a single development track will be confirmed through their reproducibility and operational data.