On September 3, 2026, Tingbo He, who leads Huawei's semiconductor business, posted a preprint to arXiv claiming that the in-development "Kirin 2026" achieves a nominal 55% increase in transistor density while cutting power at equivalent performance by 66% for the NPU, 58% for the GPU, and 41% for CPU performance cores. The claim is that LogicFolding—splitting circuits into two layers—addresses concerns that 3D stacking traps heat. However, what the paper details in depth is power and power per projected area, not the absolute value of junction temperature. The extent to which Kirin 2026 can be said to "not run hot" needs to be read carefully, broken down by operating mode and measurement conditions.
Shortening wiring and redirecting speed margin toward lower voltage
τ (tau) scaling is a principle Huawei proposes that sets a common goal of shortening the characteristic time involved in signals and processing, rather than shrinking transistor dimensions. In a peer-reviewed position paper He published in Science China Information Sciences in July, the scope was expanded across four layers: transistors, circuits, chips, and systems. While process shrinkage is one way to reduce characteristic time, the approach also touches wiring, circuit placement, memory access, and communication protocols.
The LogicFolding used in Kirin 2026 splits digital, analog, and memory circuits into two stacked active circuit layers connected via hybrid bonding. According to Huawei, there are roughly 50 million vertical interconnects, of which 10–15% carry signals. In the folded paths, wiring length was shortened by 20% for typical circuits and by up to 70% for some critical paths. In one processing block, clock wiring shrank by 28%, and the number of clock buffers reportedly fell from 43,600 to 19,000.
Shorter wiring means less capacitance C to charge and discharge each time a signal travels. In the dynamic power equation P=αCV²f, a reduction in capacitance C directly lowers power. Moreover, if the speed margin gained from shorter wiring is redirected toward lowering voltage V rather than raising frequency, power drops in proportion to the square of V.
The effect is largest in the NPU and GPU, where processing is easier to parallelize. The paper explains that the NPU configuration was expanded from the previous generation's one large core plus two efficiency cores to four large cores. At a matched 29 TOPS, operating frequency could be lowered from 1.2 GHz to 0.442 GHz and voltage from 0.85 V to 0.55 V. By contrast, CPU performance cores, which handle a higher proportion of serial processing, are harder to run at lower voltage, and the gains vary considerably depending on the workload.
Note that the figure cited in the paper—"roughly 90% for typical smartphone workloads"—refers to the share of dynamic power. It does not mean that data movement through wiring alone accounts for 90% of total power; it also includes logic gate switching.
Even on the same chip, power density reverses depending on usage
Plotting the normalized power density from Figure 1 of the preprint, with the Kirin 9030 Pro set to 1.00, by operating mode makes clear just how condition-dependent LogicFolding is. The figures use the projected area of the two layers viewed from above as the denominator, and the baseline for "equivalent performance" differs by block.
{
"type": "bar",
"title": "Power Density of Kirin 2026 by Operating Mode",
"unit": "vs. previous generation",
"categories": ["NPU · 29/70 TOPS", "GPU · 61/86.9 FPS", "CPU · HNX", "CPU · Geekbench 6"],
"series": [
{"name": "Kirin 9030 Pro", "values": [1.00, 1.00, 1.00, 1.00]},
{"name": "Kirin 2026 · Equivalent performance", "values": [0.27, 0.44, 0.76, 0.99]},
{"name": "Kirin 2026 · Peak performance", "values": [1.07, 1.26, 1.42, 1.46]}
],
"caption": "Each processing block is compared with the previous generation set to 1.00. GPU figures are for the heaviest rendering frame in a specific game. Workloads and performance metrics differ by block.",
"source": "Tingbo He, Figure 1"
}LogicFolding's thermal benefit is not constant: it appears when performance is capped at parity with the previous generation, but once peak performance is pushed, power density exceeds the previous generation's. For the NPU, capping at 29 TOPS cuts power density by 73%, but running up to 70 TOPS puts it at 1.07 times the previous generation. The GPU shows the same reversal in the heaviest rendering frame of a specific game—from 0.44 at 61 FPS to 1.26 at 86.9 FPS.
For CPU performance cores, the gap between benchmarks is even wider. On Huawei's own HNX benchmark, which uses portions of everyday mobile apps, at the same score of 1700, power fell by 41% and power density fell by 24%. But when matched at the same Geekbench 6 score of 1854, power fell by 23% while power density fell by only 1%. The headline 41% figure cannot be generalized across CPUs as a whole.
The DSP shows the opposite pattern. In Kirin 2026, the same workload was processed using 25% less power, but because the projected area shrank by 40%, power density rose by 24%. Huawei states that with Kirin 2027 prototype silicon, power was cut by 47% and power density was brought down to 0.97 times the previous generation. However, prototype silicon measurements do not imply that the product has shipped.
Calculating from published figures yields 53.5%; 1.5 micrometers is not a manufacturing node
Calculating the increase from the published figures of 155 and 238 MTr/mm² yields 53.5%, which differs by 1.5 percentage points from Huawei's claimed 55%. Moreover, this density figure is one Huawei calculated using CPP and cell height together with an assumed SoC area utilization rate of 68%. It is not a value derived by dividing the actual chip's total transistor count by a published die area, and there is no confirmation that it uses the same yardstick as other companies' published process densities.
The peer-reviewed paper states that the two Kirin chips were manufactured on the same mature process node, but does not disclose the node name or the manufacturer. The 1.5 micrometers achieved in Kirin 2026 refers to the spacing of the contacts connecting the upper and lower layers. The new preprint also contains a statement that this was "achieved using 40-nanometer equipment," but the context is the hybrid bonding process—it does not mean the transistors themselves were manufactured on a 40-nanometer node.
Huawei's stated goal of reaching "1.4-nanometer-equivalent" density by 2031 is likewise not a plan to move manufacturing to a 1.4-nanometer process, but a roadmap aiming for equivalent transistor density in the company's own high-performance chip designs. Kirin 2026 itself does not stack all of its circuits—it is a two-layer design that selectively targets the critical paths where the effect is largest, and expanding to three or more layers remains a future plan.
No temperature data yet to back up the "won't overheat" claim
Based on public materials alone, third parties cannot reproduce the claim that "Kirin 2026 doesn't overheat." The September preprint explains that the design accounts for the lower layer running several degrees hotter than the upper layer, that high-temperature blocks were arranged so as not to stack directly on top of one another, and that heat was directed to escape laterally. However, it does not disclose the junction temperature and temperature distribution during operation, nor the sample size, number of measurement repetitions, measuring instruments, or the device's cooling conditions.
The peer-reviewed July paper includes a table comparing the Kirin 9030 Pro and Kirin 2026, both measured at 25 degrees. The 25 degrees listed here is a test condition, not stated to be the junction temperature during operation. The September thermal paper is a preprint posted to arXiv and has not yet undergone peer review at this time. While usage-specific power data has grown more extensive, details of the experiments measuring temperature remain insufficient.
IEEE's IRDS notes that in 3D stacking, multiple active layers generate heat while heat dissipation pathways narrow, making it necessary to evaluate temperature differences between layers and localized hotspots. A summary of an ECTC 2023 paper published by IBM Research also states that thermal performance varies depending on stacking order and bonding method, as well as materials and cooling conditions. A reduction in power density is a strong piece of evidence, but it alone cannot determine the temperature inside a device's enclosure.
Huawei's official announcement as of May stated that a Kirin chip adopting LogicFolding would be introduced in autumn 2026. The September preprint states it is "scheduled to ship this month," but as of this writing, Huawei has not officially confirmed the name or release date of the smartphone that will carry it. Once an actual device becomes available, if performance and total power are measured under the same ambient temperature and sustained load, and surface temperature, junction temperature, and throttling can be reproduced across multiple units, it will be possible to judge how far LogicFolding has expanded the performance headroom remaining in a mature process.