On August 19, 2026, IBM announced it had connected two modular cryostats and operated them simultaneously below 15 millikelvin. The combined apparatus now exceeds 8 feet in both height and width. The news here isn't a new record-low temperature. It's that two previously independent cooling cells were run as a single low-temperature environment through which future inter-processor wiring could pass.
Scaling up superconducting quantum computers means adding not just qubits but also the measurement systems for error correction, signal lines, and inter-processor couplings—all of which must be kept cold. What IBM tested was whether the low-temperature environment outside the quantum chip, provided by the refrigerator, could be extended laterally.
What "180 times colder" actually demonstrates
15 millikelvin equals 0.015 K. Compared to the cosmic microwave background radiation of roughly 2.7 K, the ratio in absolute temperature is 180. IBM's headline figure of "180 times colder" is simply this ratio of 2.7 divided by 0.015. It doesn't mean the temperature difference multiplies quantum computing performance by 180, nor does it represent a new low-temperature milestone—sub-15 mK has long been the standard operating range for superconducting quantum machines.
What was actually verified this time is that even after connecting two cells, the system could cool to 4 K in under five days and subsequently reach below 15 mK. Rather than cooling each cell separately, IBM created a shared low-temperature environment that included the junction between them. If future systems need more pathways to route signals to other quantum processors, the spaces where cables pass through must also remain stable within the same temperature range. The demonstration stops there—the actual functioning of any inter-cell link still needs separate verification.
From cylinder to box: 0.53 square meters of wiring space
Each cell provides roughly 0.53 square meters of usable wiring area and 2.75 cubic meters of vacuum chamber volume. According to IBM, each cell's vacuum housing offers up to 12 times more wiring space than the company's widely used conventional systems. Enlarging a cylindrical cryostat designed for a single processor concentrates wiring and heat generation into one housing—making maintenance harder and requiring tighter control of crosstalk. A design using box-shaped cells arranged side by side, by contrast, allows the apparatus to expand horizontally.
Each of the two cells has its own vacuum chamber, cooling mechanism, and thermal shielding. At the junction, shields are connected stage by stage to create a protected, low-temperature tunnel through which quantum cables can pass. What IBM describes as the L-coupler is a long-distance quantum interconnect that links separate QPUs positioned roughly a meter apart within the dilution refrigerator. It's a structure designed to keep the pathway between them cold and low-noise, enabling separate chips to function as a single computing system.
The design—separating vacuum and cooling mechanisms per cell—also narrows the scope of construction work needed for future expansion. IBM explains that thermal shielding limits thermal interference between adjacent cells, allowing cooling time and temperature stability to remain consistent even as more cells are added. With conventional integrated systems, any change to the internal configuration required handling a large low-temperature space as a whole. Box-shaped cells, by contrast, could in principle be tested and swapped out one room at a time to match future processor generations. That said, what's been disclosed so far is only an early two-cell demonstration—there's no data yet on cooling performance with dozens of cells connected, nor any indication of whether maintenance can be performed on one cell while an adjacent one remains operational.
The qLDPC codes behind 288 physical qubits
The gross qLDPC code that IBM plans to make central to future error correction encodes 12 logical qubits using 144 data qubits and 144 syndrome qubits—288 physical qubits total. A 2024 study published in Nature estimated a threshold of 0.7% under a standard circuit noise model. Under a physical error rate of 0.1%, numerical simulations showed the 12 logical qubits could be preserved for roughly 1 million syndrome cycles, compared with an estimated requirement of about 3,000 physical qubits for a surface code to achieve similar results. This is a simulated projection, not a measured result from actual hardware. On a simple average, this works out to 24 physical qubits (data plus check qubits combined) protecting each single logical qubit.
For Starling, which aims to scale up to 200 logical qubits, what will most shape the physical infrastructure isn't the raw qubit count but how the control and error-signal readout pathways for each qubit are accommodated. Signal lines carry heat in from room temperature, and each cooling stage has a finite capacity to handle that heat load. The significance of expanding wiring area 12-fold isn't simply more room to place chips—it's securing space to fit the increased input/output lines that error correction requires within the refrigerator's overall heat budget.
However, a 12-fold increase in wiring area doesn't necessarily mean a 12-fold increase in cooling capacity. IBM has not disclosed the tolerable heat influx at the 15 mK stage, nor the loss per individual L-coupler. Being able to physically place wiring is a separate matter from being able to preserve quantum states while absorbing the heat generated during computation.
The resource efficiency of qLDPC codes comes with demanding wiring requirements. The研究 calls for six couplings per physical qubit, a two-layer planar graph, a low-loss second wiring layer, and long-distance couplers as hardware challenges. These requirements demand not just space to place qubits but also pathways to keep the couplings cold. The two cells and the L-coupler represent the groundwork for housing that pathway within a low-temperature space—a prerequisite for turning qLDPC's reduction in physical qubit count into an actual hardware advantage.
Simultaneous cooling demonstrated—inter-module computation still unmeasured
Successfully cooling two cells to below 15 mK simultaneously does not amount to demonstrating high-fidelity quantum information transfer. Based on press briefing coverage, Live Science reported that while IBM tested simple gate operations on Flamingo, it has not yet performed complex inter-module operations. IBM has not disclosed fidelity figures for inter-module gates, thermal load margins, continuous operating time, replacement time in case of failure, or total system power consumption. What has been confirmed so far is limited to simultaneous cooling of two connected cells below 15 mK—the implementation and fidelity of the inter-cell link, along with inter-module computation itself, remain unverified.
For comparison, it's worth noting what different experiments actually measure. Google's Willow reported, in a peer-reviewed experiment, a logical error rate of 0.143% ± 0.003% per error-correction cycle using a distance-7 surface code memory with 101 qubits. It also demonstrated that errors were suppressed by a factor of 2.14 ± 0.02 for every increase of 2 in code distance, and that logical qubit lifetime was 2.4 ± 0.3 times longer than that of the best physical qubit. IBM's latest announcement does not demonstrate qLDPC or inter-module computation, so it cannot be judged as superior or inferior to Google's surface-code memory experiment using the same yardstick.
Looking ahead: 1,000 qubits by 2027, Starling by 2029
IBM plans to mount its new Nighthawk processor in the new cells later in 2026 to expand performance testing. By 2027, the company aims to connect multiple processors using the L-coupler and build a system with at least 1,000 programmable qubits. The two cooling cells represent, within that roadmap, an early piece of infrastructure for linking multiple QPUs laterally. Whether this timeline holds can only be judged once operational quality and conditions are disclosed for the connected system.
IBM has further stated a goal for Starling: executing 100 million quantum gates using 200 logical qubits by 2029. This is not yet an achieved level of performance. Turning qLDPC's theoretical reduction in physical qubit count into an actual hardware advantage requires long-distance couplers, additional wiring, and error correction components to all function within the same low-temperature environment. What gate fidelity and operational data emerge from cells connected via Nighthawk will be the first test linking the 2027 goal of 1,000 qubits to the 2029 Starling milestone.