Belgium's research organization imec announced 3-layer wiring superconducting circuits using niobium titanium nitride (NbTiN) at the Applied Superconductivity Conference (ASC) 2026 on September 7, 2026. On the circuit side, the minimum diameter of Josephson junctions was reduced to 150nm, achieving a design density of 3.8 million junctions per cm². As a separate wiring achievement announced alongside this, imec reported shrinking 3-layer NbTiN wiring to a width of 30nm. Reading this announcement as a semiconductor "30nm node" would be a misinterpretation. What actually advanced here was the process of bringing cryogenically-operated circuits and fine wiring into a multilayer structure under the discipline of 300mm CMOS manufacturing equipment.
The distance to practical application remains substantial. A design concept published by the imec consortium in 2023 called for 16 wiring layers to pack 400 million devices per cm², operating at 30GHz. Today's 3.8 million junctions represent roughly 0.95% of that density. Separating what the 3-layer prototype circuit actually enables from what remains a design target reveals both the value and the limits of this announcement.
What the 3-Layer Circuit and 3.8 Million Junctions Actually Demonstrate
Superconducting digital circuits don't represent 0 and 1 through voltage levels like CMOS transistors. Instead, they use quantized magnetic flux pulses. Josephson junctions act as switches generating these pulses, while superconducting wiring carries them. According to NIST, these single flux quantum (SFQ) circuits can operate at speeds exceeding 100GHz. However, scaling up requires fabricating junctions at high density and with uniformity. Circuits carrying signal and power must also be integrated with clocks and memory.
The junctions imec demonstrated use a structure sandwiching thin amorphous silicon between NbTiN electrodes. On the junction-circuit side, diameter was reduced to 150nm, with wiring layers increased to three. In a separate wiring demonstration, three layers of wiring and vias were formed, with wire width narrowed to 30nm. Beyond carrying signals, wiring layers also provide space for inductors, ground planes, and resonators for clock and power distribution. The significance of adding layers lies less in increasing junctions on a plane than in connecting signal and power paths without congestion.
The figure of 3.8 million junctions/cm² is a "design density." The press announcement does not disclose the actual total number of junctions operated or the logical function of the circuit. Operating frequency and yield across the wafer remain unknown. At ASC, separate presentations addressed junction fabrication and low-temperature characteristics, as well as research on AC power delivery and failure analysis. Crossbar switches remain at the modeling research stage. As of September 9, 2026, the peer-reviewed ASC 2026 papers had not yet been published, meaning the imec press release and conference information are the only sources currently available to verify the core results. This is not an announcement unveiling a completed AI processor, but rather progress on the components and manufacturing process needed to build one.
Why Move From Niobium to NbTiN?
Niobium (Nb) has been widely used in conventional superconducting digital circuits. Its track record is extensive, but in a comparison imec presented in 2025, a representative Nb process on 200mm wafers offered a minimum feature size of 250nm. Its superconducting transition temperature was about 9K, with a back-end thermal budget of 200°C. The NbTiN platform extends wafer diameter to 300mm and shrinks minimum feature size to 50nm. It claims a transition temperature above 13K and a thermal budget above 420°C. While these figures compare against imec's own baseline platform, they clearly illustrate the rationale for the material shift.
A higher transition temperature provides more operating margin against manufacturing variation and localized heating. NbTiN also withstands higher-temperature wiring processes and can be patterned using existing 300mm equipment with 193nm immersion lithography. This is a material that moves the technology away from lab-specific small-diameter wafer processes and closer to the metrology, planarization, and multilayer wiring techniques used throughout the semiconductor industry.
However, "CMOS-compatible" does not mean designs can simply be brought into an existing CPU fab for mass production. Material management is required for NbTiN, amorphous silicon, and HZO capacitors. Furthermore, junction variability and flux trapping—invisible in room-temperature electrical testing—must be measured at cryogenic temperatures. There remains a gap between the possibility of sharing manufacturing equipment and having a completed mass-production process.
30nm Dates to June; September Presents Two Achievements Together
Arranging the public record chronologically clarifies both the origin of the 30nm figure and the scope of the September announcement.
imec's superconducting wiring progressed from a 2-layer, minimum-50nm structure in 2024 to a minimum 30nm in June 2026, and the September ASC announcement presented both the 3-layer wiring and the 150nm minimum Josephson junction circuit as achievements from the same underlying research platform.
| Timepoint | Disclosed Content | Manufacturing Significance |
|---|---|---|
| April 2023 | 16-layer, 400 million devices/cm², 30GHz design concept. Manufacturing track record: 2-layer, 50nm wiring | Presented completed vision and initial modules |
| December 2024 | 2-layer, 50nm wiring, transition temperature above 13K, critical current density above 120mA/µm² | Demonstrated key components at 300mm, within 420°C |
| June 2026 | 50nm-thick wiring narrowed to 30nm width. Transition temperature above 12K, up to approximately 200mA/µm² | Confirmed superconductivity and current-carrying capacity maintained after miniaturization |
| September 2026, junction circuit | 3-layer wiring, 150nm junctions, 3.8 million junctions/cm² | Presented multilayer junction circuit and design density |
| September 2026, wiring | 3-layer wiring and vias, 30nm wire width | Presented the fine wiring shown in June as a separate achievement from the same research platform |
The 30nm wiring had already appeared in the June 2026 International Interconnect Technology Conference (IITC) program. There, a 50nm-thick NbTiN film was patterned using 193nm immersion lithography, achieving a transition temperature above 12K and a critical current density of up to approximately 200mA/µm². In September, two achievements—a junction circuit with 3-layer wiring, and 3-layer wiring at 30nm width—were presented together as progress from the same research platform. The public record does not confirm whether the two were integrated into a single sample.
The change from 50nm in 2024 to 30nm represents a 40% reduction in line width. However, the percentage reduction in line width cannot be used to calculate areal density. In superconducting circuits, area is consumed not only by Josephson junctions but also by loops holding magnetic flux, inductors, and resonators distributing power and clock signals. Narrowing wiring also changes the critical current it can carry and its kinetic inductance, requiring dimensions and circuit characteristics to be tuned together.
The 105x Gap Between 3.8 Million Junctions and 400 Million Devices
The circuit design density of 3.8 million junctions per square centimeter announced this time is approximately 0.95% of the 400 million devices per square centimeter design target the imec consortium presented in 2023—meaning the target is roughly 105 times larger. This comparison isn't meant to diminish the current achievement. Rather, it serves as a yardstick for measuring what remains to be built to reach imec's targeted scale.
However, the two figures differ in character. The 3.8 million figure is a published achievement representing Josephson junction design density in a 3-layer circuit, while the 400 million figure is a device density that a proposed stack—combining 16 wiring layers, self-shunted junctions, and low-loss HZO capacitors—was said to enable. The scope of "device" and "junction" also may not be perfectly equivalent. Thus 0.95% cannot be called a development completion rate, but it's clear that both the process of progressing from 3 to 16 layers and the design technology for converting component density into circuit density remain to be developed.
While increasing layer count improves wiring flexibility, variations in film thickness and flatness accumulate across each layer. Vias must reliably connect between layers, and junctions must maintain their specified critical current. If magnetic flux becomes trapped in unintended locations, the circuit malfunctions. Design capability to place millions of junctions is a different metric from manufacturing yield that allows millions to operate simultaneously with the required margin. What's needed next is measurement of junction counts and yield in a functioning, large-scale circuit.
Cooling-Inclusive Advantages Will Be Determined by System Demonstration
imec touts potential advantages for superconducting technology over advanced CMOS: 100x energy efficiency, 1000x computational density, and 1000x bandwidth for distributing signals to numerous destinations. These are not performance figures measured on the 3-layer circuit announced now. They are predictions based on the company's cross-layer models and future highly-integrated platforms.
Even though superconducting wiring has near-zero electrical resistance, system power consumption doesn't reach zero. Junction switching and power delivery circuits generate heat, and the refrigerator cooling to approximately 4K consumes power on the room-temperature side. Efficiency also varies depending on which temperature stage houses memory and how the 4K computing section connects to room-temperature networking. This is why imec's systems research addresses 2.5D/3D packaging, cryogenic CMOS, and optical I/O in parallel with fine-pattern fabrication.
Design infrastructure carries equal weight. imec's 2025–2030 roadmap calls for increasing wiring from 3 to 5 to 7 layers while establishing device models and parasitic extraction methods. It also outlines a flow where, after preparing standard cells and memory macros, place-and-route is automated and timing and noise are verified. Even if 30nm lines can be fabricated, this won't become an industrial design platform unless designers can automatically place millions of junctions and predict post-fabrication operating margins.
This achievement alone cannot predict when a superconducting AI computer might be completed. The judgment criteria will be the logical functions and frequency executed by 3-layer circuits, variability and yield across the full wafer, failure rates when scaling beyond 5 layers, and total system power including the refrigerator. Only once these measurements are in hand can this platform—including its 30nm wiring—be evaluated as manufacturing technology capable of overcoming CMOS's power and interconnect constraints.