Wccftech reported that the customers for the LPDDR6/5X PHY plus memory controller developed by Chinese semiconductor IP company Innosilicon (芯动科技) include a major Korean DRAM manufacturer. This reportedly came to light at the company's high-bandwidth IP seminar held in Shanghai on July 23, 2026. In its January announcement, Innosilicon had disclosed a contract and delivery to a "major industry player" but withheld the customer's nationality and company name. If this latest information is accurate, it would mean that interface IP that had been targeting demand for domestic Chinese substitutes has been delivered to a Korean manufacturer that develops its own LPDDR6.
However, the name of the adopting company remains unknown even now. What it will be used for, whether the customer chip has taped out, and whether it actually operated at 14.4Gbps with real DRAM have not been disclosed. The presence of Samsung Electronics at the venue cannot be used as grounds to link the company name, and no direct connection has been confirmed with SK hynix's 14.4Gbps prototype chip either. To evaluate this announcement, it is necessary to separate the role of the IP from the progress of mass-production DRAM.
What Changed in Six Months Is the Outline of the Customer
Tracing Innosilicon's public information, the groundwork for LPDDR6 dates back to July 2025. When the company announced its LPDDR5/4 Combo IP for 28nm/22nm, it had already previewed the launch of an LPDDR6/5X Combo IP for FinFET processes from 12nm to 3nm in Q3 of the same year. On January 21, 2026, it announced a contract and delivery of a 14.4Gbps-compatible PHY plus controller to a major industry player, describing it as the first commercial case of Chinese-made LPDDR6 interface IP.
Wccftech reported that at the Shanghai seminar on July 23, Innosilicon described the customer as a major Korean DRAM manufacturer. According to advance information from co-host S2C, the meeting showcased a range of high-speed interfaces including LPDDR6, UALink, and PCIe 6.0. While Wccftech reported that a Korean company is using Innosilicon's LPDDR6 IP, it did not convey the scale of the contract or the target project.
"Delivery" of semiconductor IP refers to the stage where the customer receives design data and proceeds to integration and verification. It is only after passing through tape-out, prototype silicon bring-up, interoperability testing with DRAM, and customer qualification that the product makes it into mass production. What Innosilicon announced is the entry point of this long process. Even if Wccftech's report is accurate and the customer base has expanded to include an overseas DRAM manufacturer, this is not synonymous with mass-production adoption.
IP Adoption Does Not Mean Transfer of DRAM Manufacturing Technology
In an LPDDR6 system, two design blocks sit between the computing circuitry and the DRAM. The memory controller manages the order of reads and writes and refresh operations, while the PHY (physical layer) handles electrical signals, clocks, and training. What Innosilicon sells is this combination of PHY and controller—not the DRAM cells that store data or their manufacturing process.
| Stage | Main Role | What Has Been Confirmed This Time |
|---|---|---|
| Compute Core/NoC | Sends AI or CPU processing requests | Type of customer chip unknown |
| Memory Controller | Controls reads, writes, bank management, and refresh | Innosilicon delivered the IP |
| LPDDR6 PHY | Generates high-speed signals, aligns timing and signal quality | Claims up to 14.4Gbps |
| LPDDR6 DRAM | Retains data | Both Korean companies have already developed their own silicon |
Looking at this division of labor, there is no contradiction in a DRAM manufacturer evaluating an external PHY plus controller IP. There are multiple scenarios where host-side IP is needed, such as test environments for verifying DRAM characteristics, reference platforms for customers, and composite products that include a controller. That said, the use case in this instance has not been disclosed. Before speculating on whether it's Samsung or SK hynix, it would be better to first confirm whether this is for evaluation purposes or for incorporation into a shipping product.
Cadence's LPDDR6 IP also makes clear this same division of labor. The controller is provided as soft RTL that can be integrated into an SoC, while the PHY is a hard macro tailored to the manufacturing process and package routing. Therefore, the value of the IP is determined not only by logical functionality compliant with the JEDEC specification, but also by whether it can secure signal margins on a specific process and actual routing, and pass testing with the connected DRAM.
14.4Gbps Is the IP Specification; Initial DRAM Samples Are 10.67Gbps
JESD209-6, published by JEDEC in July 2025, divides one die into two sub-channels, with 12 data lines allocated to each sub-channel. Compared to the 16-bit width common in conventional LPDDR5X, LPDDR6 has a 24-bit width. It also incorporates voltage reduction at low frequencies via DVFSL, Dynamic Efficiency Mode that uses only one sub-channel under light loads, and row-level activation counting that contributes to RowHammer mitigation.
Bandwidth is determined by the product of per-pin speed and data width. Running LPDDR6 at its initial speed of 10.67Gbps with a 24-bit width yields a raw transfer bandwidth of about 32.01GB/s. This is 1.5 times the roughly 21.34GB/s achieved when running LPDDR5X at 10.67Gbps with a 16-bit width. If LPDDR6 reaches 14.4Gbps, that becomes 43.2GB/s—approximately 2.02 times the same LPDDR5X comparison.
The figure of 14.4Gbps needs to be treated separately from the actual connection track record with real DRAM. On July 24, Synopsys explained that the upper limit supported by initial LPDDR6 DRAM samples is 10.67Gbps, and confirmed read/write eye openings at that speed on actual silicon. Meanwhile, 14.4Gbps is presented as PHY capability using test equipment. Innosilicon's 14.4Gbps figure is likewise an IP specification that supports the upper end of the JEDEC roadmap, and is not a number that proves the Korean customer's mass-production product will operate at that speed.
On the DRAM side, progress is already advancing in stages. In March, SK hynix announced 16Gb LPDDR6 using a 1c process, with a base operating speed exceeding 10.7Gbps, a 33% speed improvement over previous products, and power consumption reduced by more than 20%. The company plans to complete mass-production preparations in the first half of 2026 and begin supply in the second half. Samsung, at CES 2026, presented 10.7Gbps, up to 16GB capacity, and approximately 21% improved energy efficiency compared to the previous generation. At ISSCC 2026, SK hynix presented a 14.4Gbps 16Gb chip and Samsung presented a 12.8Gbps 16Gb chip, indicating there is still a gap between the upper limits shown in research presentations and the speeds of initial products.
Competing with Cadence and Synopsys in the Design IP Market
The 14.4Gbps banner itself is not unique to Innosilicon. On July 9, 2025—the same day the JEDEC specification was published—Cadence announced the tape-out of a 14.4Gbps-compatible LPDDR6/5X PHY plus controller. The company explained that this configuration can be integrated into both monolithic SoCs and chiplets, and that it was advancing multiple projects with customers in AI, HPC, and data centers. Synopsys has also assembled a 14.4Gbps-compatible PHY, controller, and verification IP, and in July 2026 published results of a 10.67Gbps connection with actual DRAM samples.
If Wccftech's report is accurate, what Innosilicon has demonstrated as new in this market is not the top speed, but the fact that its customer base has expanded to include a DRAM manufacturer outside China. However, since the use case, selection rationale, and verification items on the Korean manufacturer's side have not been disclosed, it cannot be said that its PPA (power, performance, area) or signal quality is superior to competitors. What can be confirmed at this stage is only that Innosilicon officially announced a delivery to an anonymous major industry player, and that Wccftech reported that customer to be a major Korean DRAM manufacturer.
Care is also needed regarding the language around process support. Innosilicon states that it supports processes from 55nm to 3nm across the company as a whole, and Wccftech reported that the venue exhibit covered 28nm to 3nm. However, in the company's 2025 roadmap, 28nm/22nm was designated for LPDDR5/4, while LPDDR6/5X was separately designated for FinFET processes from 12nm to 3nm. 3nm compatibility refers to the scope of IP supply—that the PHY can be ported to manufacturing processes such as those from TSMC or Samsung. It does not mean that 3nm LPDDR6 chips can be manufactured domestically in China.
Three Pieces of Evidence to Connect Adoption to Mass Production
For this case to develop into a shift in the balance of power in the LPDDR6 IP market, three pieces of evidence are needed. The first is confirmation from the customer side, or an explanation—even while keeping the company name withheld—of the use case and reasoning for adoption. The second is tape-out and silicon bring-up on the customer's process. The third is interoperability results connecting actual DRAM from Samsung, SK hynix, Micron, and others, along with the mass-production timing of the final product.
The destination for LPDDR6 is not limited to smartphones. In April 2026, JEDEC revealed that it is developing an x6 sub-channel to increase capacity for data centers, an interchangeable LPDDR6 SOCAMM2, and LPDDR6-PIM, which performs computation within memory. In AI inference, power and bandwidth for moving data to computing units tend to be constraining factors, and the move to expand low-power DRAM into servers is also expanding the market for IP vendors.
Innosilicon has publicly announced the delivery of IP to an anonymous major industry player, and Wccftech reported that one of the delivery destinations is a major Korean DRAM manufacturer. What will change this assessment is not a logo at the next trade show, but interoperability results at 10.67Gbps or 14.4Gbps on customer silicon, and a date marking the start of mass production.