In 1968, when Gordon Moore and Robert Noyce founded Intel, the company's only products were memory chips. Intel brought commercial DRAM to market in 1970, and remained a memory company well into the early 1980s. Then, in 1985, faced with an overwhelming mass-production offensive from Japanese manufacturers, Intel decided to exit the DRAM business. At the time, Japan's share of global DRAM production had reached 90%, and memory became synonymous with a "losing battle" for Intel.
For a long time, this exit has been cited in semiconductor industry management studies as the "correct decision." Memory is a commodity—hard to differentiate and prone to being dragged into price wars. By concentrating its resources on microprocessors, Intel built the massive moat known as the x86 architecture. This decision, which even became a Stanford Graduate School of Business case study, came to symbolize the industry wisdom that "you should flee from commodities."
Forty years later, the situation has reversed.
The bandwidth demands of AI accelerators have exploded, and High Bandwidth Memory (HBM) has become the bottleneck for every AI chip. Although HBM accounts for only about 8% of total DRAM bit shipments, it generates roughly 30% of DRAM revenue. Supply is oligopolized by just three companies—SK hynix, Samsung, and Micron—and 2026 HBM production capacity was already nearly sold out at the start of the year. Micron has signed five-year long-term supply contracts with 16 strategic customers, with cumulative minimum price guarantees totaling approximately $100 billion.
Gartner forecasts that combined DRAM and SSD prices will rise 130% by the end of 2026. Tan himself, speaking at a Cisco Systems-hosted conference in February 2026, said, "There's no relief as far as I know," revealing that major memory suppliers had told him there would be "no relief until 2028."
Memory is no longer a commodity.
Three Moves Have Converged Simultaneously
What makes Tan's remarks noteworthy is not just the words themselves, but the fact that concrete actions are unfolding in parallel. In the first half of 2026 alone, Intel took three significant steps related to memory.
The First Move: The XBM Patent. Filed on December 26, 2024, and published on July 2, 2026, this patent describes a new architecture named "cross-batch memory (XBM)." Whereas conventional HBM stacks DRAM dies on a silicon interposer and communicates with the processor via an ultra-wide 1,024-bit parallel interface, XBM eliminates the interposer entirely. The DRAM cells themselves are built as thin-film transistors within the back-end-of-line (BEOL)—the metal wiring layers above the transistor layer—and data is transmitted via a UCIe (Universal Chiplet Interconnect Express) serial link (32 GT/s). Each die is said to have a capacity of roughly 1.5 GB, yielding 12 GB with an 8-layer stack, expandable up to 16 layers. It incorporates built-in self-repair (BISR) mechanisms and spare channels, addressing stacking yield issues at the design stage.
The Second Move: ZAM Joint Development. On February 2, 2026, Intel signed a collaboration agreement with SAIMEMORY, a subsidiary of SoftBank, aimed at commercializing Z-Angle Memory (ZAM). ZAM employs a 9-layer stacked structure using fusion bonding, thinning the silicon substrate between each layer to roughly 3µm to reduce TSV resistance. According to data presented at VLSI Symposium 2026, it achieves a bandwidth density of approximately 0.25 Tb/s/mm², reaching roughly 5.3 TB/s per 10GB module—more than double the roughly 2 TB/s per stack offered by HBM4. Energy consumption per data movement is said to be under 0.7 pJ/bit. Japan's Ministry of Economy, Trade and Industry (METI) is providing subsidies of up to ¥3.8 billion, with prototypes targeted for fiscal year 2027 and commercialization for fiscal year 2029.
The Third Move: The Hiring of Seok-Hee Lee. On June 18, 2026, Intel appointed Lee as Executive Vice President of Intel Foundry. From 2000 to 2010, Lee worked in Intel's Portland Technology Development division on process integration spanning 130nm to 32nm, earning three Intel Achievement Awards. He subsequently led HBM development as CEO of SK hynix, and also spearheaded that company's acquisition of Intel's NAND business in 2020. In other words, the executive who once oversaw the purchase of Intel's memory business is now the one returning to Intel.
| Metric | Conventional HBM | Intel XBM (Patent Stage) | ZAM (SAIMEMORY Joint Development) |
|---|---|---|---|
| Interface | 1,024-bit wide parallel (via silicon interposer) | UCIe serial 32 GT/s (no interposer required) | Fusion-bonded TSV, direct Z-axis connection |
| DRAM Cell Location | Front-end (within silicon substrate) | Back-end-of-line (BEOL metal layers) | Conventional DRAM cells (novel bonding method) |
| Bandwidth per Stack | ~2 TB/s with HBM4 | Unpublished (operates at UCIe spec ceiling) | ~5.3 TB/s (10GB module) |
| Stacking Structure | 8 or 12 layers (micro-bump bonding) | 8 layers (expandable up to 16) | 9 layers (fusion bonding, ~3µm inter-layer silicon) |
| Commercialization Target | In mass production (HBM3E); HBM4 from 2026 onward | 2030 and beyond | Prototype FY2027, commercialization FY2029 |
The Weight Behind "Stacking Memory on Top of the CPU"
On a podcast, Tan said: "I think CPU and memory, I think there are a lot of ways we can really do stacking together. And also try to find some new architecture for memory. I think in some way the memory, a lot of innovation are not there. So, there is some really good area."
This statement carries weight beyond mere rhetoric. In current AI accelerators, HBM stacks are already placed within the same package as the logic die—packaging and memory have already become, structurally, a single problem. Given that Intel, through its foundry business, has invested in advanced packaging (Foveros, EMIB, etc.), the technical foundation for integrating memory within a package already exists.
The Memory-on-Package (MoP) structure described in the XBM patent points directly in this direction. While conventional MoP adds 300–350µm of Z-height, Intel's design uses a "reversed overhang" structure to reduce this, eliminating the need for a stiffener (anti-warping component). Power to the DRAM is also supplied directly from the voltage regulator. The goal is to make the entire package smaller and cheaper. If realized, memory would no longer be a "separately purchased component to be mounted," but would instead be designed as "part of the CPU."
That said, Tan added an important caveat. He did not clarify whether this project is an official Intel strategic initiative or a personal investment through Walden International, the venture capital firm he founded. His words—"We are not ready to unfold it"—reveal not only the scale of the ambition but also the ambiguity of the commitment.
$20 Billion in Ammunition, $10 Billion in Losses
On August 10, 2026, Intel increased its equity offering—initially set at $15 billion—to $20 billion, pricing shares at $95 each. Net proceeds came to approximately $19.7 billion. The stated use of funds is "general corporate purposes, including capital expenditures and working capital." Notably, Tan's memory comments were published on August 12—the very closing date of this offering.
Intel's Q2 2026 earnings showed revenue of $16.1 billion (up 25% year-over-year), with the Data Center and AI segment reaching $6.3 billion (up 59% year-over-year)—the company's highest growth rate in roughly 15 years. Meanwhile, the foundry business posted losses exceeding $10 billion in 2025, and winning external customers remains a work in progress.
Re-entering the memory business would require, at minimum, building at least one dedicated memory fab, developing competitive process technology, and catching up to the manufacturing yields that SK hynix and Samsung have built over decades. Technical risks also remain: XBM relies on BEOL DRAM, a technology not yet in mass production, and the UCIe interface is already operating at its spec ceiling of 32 GT/s.
Third Time's the Charm, or Fourth Time's the Retreat?
This is not Intel's first attempt to return to memory. There was RDRAM in the late 1990s, and 3D NAND and Optane (3D XPoint) in the 2010s. Each ended in withdrawal. Optane alone racked up cumulative losses of roughly $6.8 billion between 2016 and 2020.
This time, however, the structure is different. Intel is not aiming to mass-produce conventional DRAM or NAND and compete on price with SK hynix and Samsung. Both XBM and ZAM are architectural proposals that fundamentally rebuild the cost structure underlying existing HBM—the silicon interposer, micro-bump bonding, and ultra-wide wiring. Rather than entering the existing arena, this is an attempt to reshape the arena itself.
Even so, a patent is not a product. ZAM's prototype is slated for fiscal 2027, and XBM's commercialization for 2030 or later. In the meantime, HBM4E and HBM5 will emerge, and SK hynix and Samsung will fight back with their own cost-reduction technologies—standardized chiplets, UCIe, fan-out packaging. The barriers of platform compatibility and software ecosystems remain high as well. Today's AI accelerator ecosystem is optimized around HBM architecture, centered on NVIDIA, and any shift to alternative memory would require coordination across the entire industry.
Perhaps Tan's remark—"We are not ready to unfold it"—reflects caution. Or perhaps nothing has truly been decided yet. The company that invented DRAM is, forty-one years later, reconsidering that very domain. Whether this third attempt becomes a fourth retreat will be revealed by the concrete investment decisions made over the next two years.