Intel has, for the first time, put specific yearly milestones on when its advanced packaging business built around EMIB-T will start generating meaningful revenue. CFO David Zinsner, speaking at the Deutsche Bank Technology Conference on August 26, 2026, laid out a timeline: revenue growth beginning in the second half of 2027, the business becoming a steady contributor in 2028, and full-scale ramp in 2029. EMIB-T itself is already moving into factories and customer designs, so 2029 doesn't mark when the technology will be finished. The real question for Intel isn't whether it can build large AI packages—it's whether it can repeatedly manufacture customer designs at volume and convert that into external revenue and profit.
From 2026 Customer Onboarding to 2027 Revenue Growth
Zinsner said advanced packaging could generate several billion dollars annually per customer, with a gross margin of 40% and an operating margin of 30%. He framed this as a capital-light alternative to front-end wafer fabrication, capable of delivering strong returns on invested capital. He did not disclose customer names, contract values, or backlog. This is not a report of confirmed orders—it's management's picture of what the business could look like once it matures.
Advanced packaging could also become Intel Foundry's first real transaction with external customers. A customer could outsource compute die fabrication elsewhere while still handing assembly and testing to Intel. That would let Intel prove its delivery timelines, production yields, and quality—and eventually pitch its advanced-node wafer fabrication services as well. This is why Zinsner describes packaging as a gateway to front-end orders.
At its January 2026 earnings call, Intel said it was working to improve EMIB and EMIB-T quality and yield ahead of a customer-driven launch later that year. Combined with the August update, the rollout of the technology and the ramp of revenue break down as follows:
| Timing | Stage Intel Described | What It Signals |
|---|---|---|
| 2017 | Original EMIB enters mass production | Base technology and manufacturing experience built on Intel's own products |
| 2025 | EMIB-T introduced | TSV-equipped bridge deployed in products and customer designs |
| Late 2026 | Support for customer onboarding begins | Quality and yield refined; prototyping and qualification advance |
| Late 2027 | Revenue begins to grow | Qualified projects move to volume shipment and revenue |
| 2028 | Business becomes a steady revenue contributor | Ongoing projects contribute across multiple quarters |
| 2029 | Business reaches full scale | External packaging becomes a business of real size |
This timeline doesn't represent a one-year delay. "Customer onboarding" in late 2026 and "revenue growth" in late 2027 are different milestones. Customers must finalize designs combining compute dies, HBM, and substrates, verify electrical and thermal performance in prototypes, and pass reliability testing before moving to volume production. Only once a product meets shipping requirements can Intel begin booking recurring revenue.
The design environment is also part of commercialization. The EMIB-T-compatible flow that Synopsys announced in July 2026 handles initial bump and TSV placement, UCIe and HBM routing, and power, thermal, and signal analysis from die to bridge to substrate—all within a single environment. Even if Intel provides the manufacturing process, volume orders won't grow unless customers can finalize designs and verify manufacturability in advance. The time until 2029 includes not just factory capacity expansion but also the maturation of this design ecosystem.
EMIB-T Adds a Power Path to the Silicon Bridge
EMIB embeds a small silicon bridge into the packaging substrate that carries multiple dies, connecting adjacent logic dies and high-bandwidth memory (HBM) at high speed. Rather than covering the entire package with a large silicon interposer, it uses silicon only where fine wiring is needed. Intel moved the original EMIB into mass production in 2017, gaining experience through a mix of its own products and externally sourced silicon.
EMIB-T runs through-silicon vias (TSVs) through that bridge. While signals travel horizontally between dies, power is routed vertically from the bottom to the top of the bridge, easing pressure on the signal routing at the package surface. As HBM generations advance and power consumption of compute dies and memory increases, fitting signal and power lines into limited area becomes harder. TSVs aren't simply a component added to enable bigger packages—they're a means of reliably delivering power to packages that have already grown larger.
Intel's official roadmap progresses from roughly 4x reticle size, 8 HBM stacks, and 12 EMIB bridges in 2023, to over 8x, 12 HBM stacks, and over 20 EMIB bridges in 2026. By 2028, the plan calls for packages exceeding 12x reticle size with more than 24 HBM stacks and over 38 EMIB bridges. The more compute dies are arranged beyond what a single lithography exposure can cover, the more bridge count and power delivery management grows in complexity. Thermal management and substrate warpage must also be controlled simultaneously. This isn't simply a race to set package-size records.
Why 40% Gross Margin Isn't a Proven Track Record
Intel Foundry posted revenue of $17.826 billion in 2025, but external revenue was only $307 million. The vast majority of the rest came from internal transactions with Intel Products. The segment posted an operating loss of $10.318 billion. In the second quarter of 2026 as well, against revenue of $5.765 billion—including internal transactions—the segment recorded an operating loss of $2.089 billion.
These losses cannot be directly compared to the 40% gross margin Zinsner cited for advanced packaging. The Intel Foundry segment combines advanced-node R&D, wafer fabrication, internal assembly, and external customer services all together. Intel hasn't separately disclosed current revenue, gross margin, or operating margin specifically for advanced packaging on its own. Customer count and backlog also remain unknown. The 40% figure isn't a track record from an existing business—it's a target for after projects reach scale.
This disclosure gap will shape how the business gets evaluated from 2027 onward. Even if external Foundry revenue grows, EMIB-T's profitability can't be measured unless the contributions of wafer fabrication and packaging are separated. Only when customer-side mass production announcements, Intel's breakdown of external revenue, and profit growth relative to capital expenditure all come together will the 40% target become verifiable.
While Intel Waits to Ramp, TSMC Moves to 14x CoWoS
Rival TSMC is already producing CoWoS packages at 5.5x reticle size in 2026. By 2028, it plans to expand to 14x, accommodating roughly 10 large compute dies and 20 HBM stacks, and aims to exceed 14x by 2029. Since Intel is also targeting over 12x reticle size and more than 24 HBM stacks by 2028, both companies will be pushing the limits of mass-produced giant AI packages around the same time.
However, reticle multiplier and HBM count alone don't determine superiority. EMIB-T uses localized silicon bridges, while CoWoS integrates dies and HBM on interposers using multiple approaches. Different structures and die dimensions mean cost and yield can vary even at the same multiplier. HBM generations and test conditions also aren't aligned between the two. What Intel needs to demonstrate isn't a prototype of the largest possible package—it's a track record of repeatedly shipping different customer designs on the same delivery timelines and quality standards.
The 2029 full-ramp forecast doesn't guarantee Intel will catch up to TSMC by that point. TSMC is already mass-producing CoWoS and can advance customer designs toward its 14x version by 2028. Intel still has work ahead: transferring the EMIB experience it built on its own products to external customer qualification, while securing substrates and HBM and improving yield on large packages. This operational capability, more than roadmap numbers, will determine order flow.
HBM Integration and DRAM Manufacturing Are Different Jobs
When Intel brought in former SK hynix CEO Seok-Hee Lee to lead Intel Foundry, some speculated this signaled a return to memory manufacturing. But the scope of responsibility Intel outlined in June 2026 covers advanced packaging, system integration, and back-end technology development and manufacturing. At the August conference, Zinsner also dismissed the idea of returning to DRAM manufacturing, instead pointing toward developing products and architectures that ease memory constraints in collaboration with the three major memory makers.
DRAM makers manufacture wafers with formed memory cells and stack them as HBM. What Intel handles with EMIB-T is connecting that HBM to compute dies and making power, signal, and thermal management work together as a single product. While there's overlap in the required equipment, yield management, and customer relationships, the entry point into the business differs. Lee's experience could help with co-design alongside HBM makers and management of large-scale mass production, but it doesn't mean rebuilding DRAM fabs.
Intel's advanced packaging strategy will face its first real evaluation based on whether external revenue grows in the second half of 2027 and whether it becomes an ongoing contributor in 2028. If Intel can align customer qualification, yield, substrate and HBM supply, and design flows during that window, EMIB-T will move from a technology portfolio item to a revenue-generating business. 2029 isn't the finish line—it's the year Intel has promised that this transition will show up in the numbers.