Intel CFO David Zinsner said on August 26 at a Deutsche Bank technology conference that defect density on the company's next-generation "Intel 14A" process is tracking better than its internal target curve. He said the pace of defect reduction is faster than on past nodes, with progress not seen since the 22nm node. He also said Intel's product division has moved into designing products that will use 14A, and conversations with external customers have shifted from reviewing process data to discussing supply volumes. The company's 2028 mass production plan remains unchanged. What's new is that process improvement, product design, and customer discussions have all become concrete around the same time.
"Best since 22nm" refers to the rate of improvement, not the current defect level
What Zinsner compared to 22nm was not the current absolute defect density of 14A. According to a transcript of the official briefing published by Tom's Hardware, 14A is outperforming the target curve Intel set for itself, and the pace of defect reduction is better than on past nodes. Intel did not disclose an absolute D0 figure this time.
D0 is a process metric that measures how many defects exist per unit area on a wafer. Even with the same D0, a larger die has a higher probability of encountering a defect. The final yield also depends on whether the circuit has redundancy and whether it meets product specifications such as operating voltage and frequency.
What can be inferred from these remarks, then, is that the pace of learning the process and eliminating defect causes is faster than Intel's internal plan. It does not mean that 14A products have reached the same yield or cost level as 22nm products. The slope of the defect reduction curve and the proportion of dies usable for mass production are two separate matters.
| Signal from Intel | What we now know | What remains unknown |
|---|---|---|
| Defect reduction curve | Outperforming internal targets, improving faster than past nodes | Absolute D0 value, layers covered, wafer-to-wafer variation |
| Design of Intel's own products | Multiple future products being designed to use 14A | Product names, die configuration, launch timing |
| Talks with external customers | Progressed from data review to questions about capacity and supply | Customer names, design wins, contracted volumes |
The three signals carry different weight. The defect curve is an internal assessment of process development, while the design of Intel's own products reflects internal demand within the company. Customer capacity discussions are evidence that talks have become concrete, but they are still a step removed from revenue-generating contracts.
The limits of comparing across generations: 22nm versus 14A
Intel's 22nm node introduced 3-D Tri-Gate transistors in 2011 and entered high-volume manufacturing in 2012. It was the node that carried a major shift from planar to FinFET transistors into mass production, which makes it an understandable reference point for Intel to cite as a success story.
The changes involved in 14A are a different matter. Intel is combining its second-generation gate-all-around transistor, "RibbonFET 2," with "PowerVia," which delivers power from the back side of the wafer. According to Intel's internal analysis as of April 2025, compared to 18A, this combination is expected to deliver 15-20% higher performance at the same power, or 25-35% lower power consumption at the same performance, along with up to 30% higher chip density. These are not measured values from actual 14A products.
That said, 14A is not a node that starts an entirely new manufacturing approach from scratch. Because it advances the gate-all-around transistor and backside power delivery introduced in 18A to a second generation, Intel can carry forward process data and manufacturing experience gained from the previous generation. The faster defect reduction may reflect not only 14A's own progress but also the effect of having already worked through difficult challenges with 18A.
The inspection environment has also changed since the early 2010s. As lithography methods, measurement equipment, and defect classification methods change, what counts as a "defect" may not even match between generations. Tom's Hardware also pointed out that the way defects are counted may not be the same between 14A and 22nm, and that defect density does not directly translate to product yield. It is reasonable to read the "best since 22nm" comparison as Intel's self-assessment for managing its own process development.
Intel's product division has begun designing for 14A
A signal closer to commercialization than the process curve is that Intel's product division is designing products for 14A. Zinsner said the company's internal product teams are demanding when it comes to evaluating manufacturing technology, and the fact that those teams are moving forward with designs has boosted confidence.
This move is consistent with the most recent Form 10-Q for the second quarter of 2026. Intel stated in that filing that it decided to complete 14A development during the quarter, and that multiple future products are being designed to use 14A. The company is also moving forward with manufacturing expansion projects, planning risk production in the second half of 2027 and mass production in 2028 for its own products.
The start of design work signals that the teams building the circuits have determined they can incorporate the process's performance, power consumption, and area into product plans. That said, Intel has not disclosed product names or tape-out timing. It also remains unclear how large the tiles using 14A will be, or whether they will be combined with tiles made by external foundries in the same package. Beginning design work is not a guarantee of manufacturing success, but it is a precondition for moving beyond manufacturing-division targets and into an actual product process.
Customer interest has shifted from data to supply volume
Conversations with external customers have also changed. According to Zinsner, CEO Lip-Bu Tan and others meet with customers weekly, and the discussions have moved from reviewing process data to questions such as "how much capacity can we get" and "what will supply look like." Customers would not be able to ask about the wafer volumes they need without having already considered the die area and launch timing for their candidate designs. This appears to represent a more concrete stage than initial sales evaluations.
However, asking about capacity is different from reserving it. Intel has not disclosed customer names or design wins. Wafer volumes and long-term contracts also remain undisclosed. The Q2 10-Q states that the scale and pace of equipment expansion for 14A will be determined based on Intel's own product roadmap and committed demand obtained from key external customers. The "confidence in customers" described at the briefing has not yet translated into the committed demand that Intel itself has set as a condition for capital investment.
This gap matters for the profitability of Intel Foundry. In its 2025 Form 10-K, Intel explained that securing the economics of leading-edge nodes requires wafer volumes beyond its own products. At the time, it had not secured a major external foundry customer for any node, and even noted the possibility of discontinuing subsequent leading-edge nodes if it failed to secure one with 14A.
In the second quarter of 2026, Intel Foundry posted external revenue of $293 million and an operating loss of $2.089 billion. While external revenue increased from $22 million in the same period a year earlier, the main driver of that increase was Altera being deconsolidated and becoming an external customer. Whether 14A's capacity discussions advance into design wins is also a question of whether Intel can change this loss structure alongside its technology roadmap.
Three things to verify before 2028 mass production
About one year remains before risk production begins in the second half of 2027, and about two years remain before mass production launches in 2028. While today's remarks revealed momentum in defect reduction, three concrete results are needed to solidify the assessment.
First, Intel itself needs to disclose an absolute D0 value along with the measurement conditions. Second, it needs to show what proportion of products actually designed for 14A—not just test structures—meet specifications including voltage and frequency. Third, external customers need to publicly announce design wins or capacity contracts, complete with names and product plans.
If the pace of defect reduction continues, if Intel's own products meet specifications during risk production in 2027, and if external customers sign contracts for 2028 mass production capacity, then 14A will have translated its internal success curve into products and revenue. The comparison to 22nm will truly carry weight only once all three of these move in the same direction.