On August 24, 2026, Futurum Group published a report produced in collaboration with Intel explaining how the next-generation process node "Intel 18A-P" affects CPU designs such as Diamond Rapids. The headline figure was a "roughly 30% frequency improvement at about 0.5V," measured on production silicon. However, this is neither a comparison of 18A-P against 18A, nor a measure of product-level performance for Diamond Rapids or Nova Lake against current CPUs. Three distinct things need to be separated: the effect of moving from FinFET to GAA transistors and backside power delivery, the improvements 18A-P adds on top of 18A, and the performance of finished products.
The 30% at 0.5V Is a Core Comparison Against FinFET
The source of the 30% figure is a peer-reviewed paper presented by Intel engineers at the IEEE/JSAP Symposium on VLSI Technology and Circuits in June 2026. Intel reported that a CPU core using RibbonFET and PowerVia showed roughly 30% higher frequency at about 0.5V compared to a FinFET design. This was a measurement comparing cores of the same class at matched supply voltage—not a measurement of generational differences in microarchitecture.
Intel's current platform materials attribute this 30% figure to Intel 18A. Futurum Group further noted that the measurement data came from production silicon of the Core Ultra Series 3 ("Panther Lake"), manufactured on 18A, covering thousands of wafers and roughly 60,000 dies. The firm received a 48-minute briefing from Intel Fellow Eric Fetzer and others on July 20, 2026. That said, the report was produced in collaboration with Intel and is not a third-party benchmark. Neither the product name on the FinFET side, nor raw distribution data, nor error margins have been disclosed.
The reason the gap widens at low voltage is that circuit delay is dominated by the transistor. Near 0.5V, the margin between supply voltage and threshold voltage is small, so transistor switching takes longer. Because RibbonFET's gate wraps around the channel on all sides, it achieves stronger electrostatic control than FinFET, making it easier to use a lower threshold voltage. PowerVia delivers power directly from the back of the wafer, reducing the voltage lost in the power distribution network. This is the operating point where faster devices most readily translate into higher core frequency.
About 0.5V is a low operating point that prioritizes power efficiency—not the condition used to measure the maximum boost clock of server or desktop CPUs. The 30% figure suggests a design that maintains the same frequency at lower power under low voltage, or the potential to use a low-voltage range that was previously hard to exploit. It cannot be read as meaning the entire product becomes 30% faster.
Four Numbers That Show What 18A-P Adds
Intel 18A-P is a derivative process that refines 18A, which already introduced GAA and backside power delivery. Intel has disclosed that 18A-P entered risk production in June 2026. The figures measuring the improvement over 18A are not the 30% figure; rather, they are broken down by target and condition as follows.
| Intel's Stated Figure | Comparison and Condition | Scope Measured |
|---|---|---|
| Over 9% performance gain | 18A-P vs. 18A, same power, 0.75V | Placed-and-routed Arm core sub-block |
| Over 18% power reduction | 18A-P vs. 18A, same performance, 0.75V | Same Arm core sub-block |
| About 12% frequency gain | 18A-P vs. 18A, same leakage | Front-end including transistors and lower-layer interconnect |
| Over 10% frequency gain | Equivalent capacitive load | Performance-oriented devices and critical paths using Power Boost |
The 9% and 18% figures represent 18A-P's improvement under two conditions: equal power and equal performance. The 12% figure is not the clock speed of the entire CPU core but a front-end metric. The over-10% figure for Power Boost also does not apply uniformly to all circuits on the chip. Adding these four figures together does not yield an overall performance improvement rate for 18A-P.
Power Boost connects front-side contacts and backside direct contacts to PowerVia. In Intel's measurements, compared to 18A, NMOS drive current improved by about 5% and PMOS by about 16%, while external resistance dropped by 20% and 12%, respectively. Designers can selectively place these high-performance devices along the paths that determine frequency. The number of low-power-oriented devices has also increased, with logic threshold voltage options expanding from four pairs to five or more. The advantage of 18A-P lies less in a single large number and more in the expanded set of options for tuning speed and power on a per-circuit basis.
18A-P is design-rule compatible with 18A, making it easy to reuse existing IP and design flows. However, simply porting an 18A-targeted design does not automatically confer the maximum benefit of Power Boost. Which paths use the new devices is a decision made by the design team. Compatibility eases the burden of migration, but it does not guarantee the same yield or the same product launch timing.
At Higher Voltage, Interconnect Matters More Than Transistors
Raising the supply voltage speeds up transistor switching. As a result, the proportion of time signals spend traveling through interconnect increases, making it harder to translate device improvements gained at low voltage into core frequency. Near the maximum clock range, in addition to interconnect resistance and capacitance, instantaneous voltage drops and heat generation also become constraints.
PowerVia also works at this higher-voltage end. In Intel 18A's placed-and-routed cores, worst-case dynamic voltage drop was reduced to roughly one-tenth compared to front-side power delivery on Intel 3. Intel states that this margin can be used to raise maximum frequency by 5–6%, or to lower dynamic power by more than 15%. This is a comparison between the power delivery networks of 18A and Intel 3—it is not a gain that 18A-P adds on top of 18A.
18A-P also modifies the interconnect. Futurum Group's report explains that adding two coarse-pitch metal layers on top increases frequency by 3% at 1.1V and by 2% at 0.65V, while also reducing power by 2%. What the original VLSI paper's summary shows is design-stage analysis, not real silicon—and it is not a result measured on Diamond Rapids. Rather than further altering the transistors, this is a measure aimed at reducing the resistance and capacitance of signal paths.
There is a separate set of figures for thermal performance. Intel states that with 18A-P, it raised the thermal conductance of the junction stack by about 50%, and combined with a thermally aware design flow, improved thermal resistance by 20–40% compared to 18A. In an evaluation at a high power density of 1,500 W/cm², the temperature rise was reduced by up to 40%. This does not mean the CPU's average temperature drops by 40%, but for circuits where localized heat limits maximum frequency, it provides margin for sustaining performance.
Diamond Rapids Is Confirmed; Nova Lake Remains at the Collaboration-Report Stage
At Hot Chips 2026, Intel officially announced that the next-generation Xeon "Diamond Rapids" will use 18A-P for its core chiplets. It will feature up to 256 cores and 1.28GB of last-level cache, with 16-channel memory reaching up to 12,800 MT/s. The more cores packed into a single package, the tighter the constraints on limited power allocation and localized heat generation become—making the ability to selectively use 18A-P's low-voltage and high-performance devices highly significant.
Even so, Intel has not disclosed Diamond Rapids' frequency or TDP. Per-SKU performance and shipping timing also remain unannounced. The start of 18A-P risk production indicates progress toward refining manufacturability on production lines, but it is distinct from the start of high-volume manufacturing or customer shipments. It is not yet possible to predict Diamond Rapids' benchmark results from the 30% or 9% figures.
Even more caution is warranted regarding Nova Lake. Futurum Group's Intel-collaboration report states that Diamond Rapids and Nova Lake are planned to deliver the initial gains of 18A-P. However, the primary Intel public materials confirmed for this article have not officially specified the Nova Lake product name, which tiles will be made on which node, or a launch timeframe. The "planned" language in the collaboration report is a useful indicator of product plans, but it does not amount to confirmed public specifications.
Ultimately, whether 18A-P succeeds will be judged by product-level numbers. For Diamond Rapids, that means checking per-SKU frequency and TDP, and measuring single-core and all-core performance within the same power envelope. For Nova Lake, the starting point will be Intel officially disclosing the product name, tile configuration, and node used. The 30% figure at 0.5V will prove its worth only when it can be converted into either performance or power savings within such product-level conditions.