On September 22, IonQ announced that it had developed and tested a decoder capable of performing quantum error-correction decoding in real time using only the 12 cores of a MacBook Pro equipped with Apple's M4 Max chip, calling it the "industry's first end-to-end real-time quantum error correction decoder." The largest configuration involved 408 logical qubits in a circuit containing more than 550,000 T gates. However, the input was simulated error data generated by IonQ from a noise model—no actual quantum computer was used. So why can processing that Google and Riverlane have chased with dedicated high-speed circuits be handled in time by a laptop CPU? And under what specific conditions from the paper were the figures cited in the press release actually measured?
IonQ's decoding test for 408 logical qubits
The technical basis for the announcement is a preprint posted to arXiv titled "Real-time decoder for a MegaQuOp quantum computer using a single CPU" (arXiv:2608.25027). The authors are Min Ye, Andrii Maksymov, and Nicolas Delfosse, all affiliated with IonQ. Version 1 was submitted on August 25 and version 2 on September 3—both pre-peer-review preprints—and the press release followed roughly four weeks later. The phrase "industry's first" comes from IonQ's press release; the paper itself does not use this term.
In quantum error correction, a classical computer continuously reads clues about errors occurring in qubits (the syndrome) and estimates where those errors happened. This estimation process is decoding, and it must run in parallel with the quantum computation. If decoding falls behind, unprocessed information piles up, forcing the quantum computation to wait. In the worst case, the entire computation slows down exponentially.
The paper's notion of "real time" means that decoding keeps pace with the rate at which error information is generated, avoiding a processing backlog that would halt computation. Even so, when delays do occur, waiting cycles are inserted, and the resulting extension of computation time is measured as "stretch."
The evaluation procedure was as follows. For three types of benchmark circuits, the paper generated error information using a circuit-level noise model modeled on IonQ's Walking Cat architecture. This data was then decoded using the 12 cores of a 2024 Apple M4 Max chip (in a MacBook Pro). The trade publication The Quantum Insider also explicitly noted that the test was not run on an actual operating quantum computer.
The largest configuration, the Heisenberg n266 circuit, allocates 408 logical qubits across 68 Q70 memory blocks (each holding 6 logical qubits) and 20 CH2 magic state factories—88 blocks in total. The assumed physical qubit count is 11,680. Dividing this by the number of logical qubits gives roughly 28.6 physical qubits per logical qubit (11,680 ÷ 408, calculated by the editors), though this figure includes the factories and is therefore distinct from the efficiency of the code itself. As a measure of the scale of logical operations, the paper cites 555,130 T gates and 1,318,310 logical measurements. Noting that conventions for counting "logical gates" vary, the paper lists both figures side by side.
Tracing "31.5 million operations" and "0.02%" back to the paper's tables
The press release stated that these circuits performed "more than 31.5 million individual quantum operations." This figure of "31.5 million" corresponds, in Table 1 of the paper, to the total number of syndrome extraction cycles for the Heisenberg n266 circuit—31,548,792—a number distinct from a count of operations.
This figure of 31,548,792 is the sum of synchronized cycles across all 88 blocks, and moreover, it is a scheduled value assuming zero decoding delay. Changing the error rate settings can push this figure as high as 38,704,160 for the same circuit. Readers who want to know the actual number of logical operations should instead look at the T-gate and logical measurement counts discussed in the previous section.
Another figure concerns the extension in computation time. The press release stated that real-time error correction was maintained with a "minimum stretch of 0.02%," characterizing this as performing millions of operations without delaying execution time. Arranging the values from Tables 2 through 4 of the paper produces the following:
| Circuit | Logical Qubits | Assumed Cycle Time | Error Rate 0.01% (p=10⁻⁴) | Error Rate 0.05% (p=5×10⁻⁴) |
|---|---|---|---|---|
| MIPT | 102 | 1 ms | 0.24% | 11.53% |
| Heisenberg n64 | 102 | 1 ms | 0.18% | 10.25% |
| Heisenberg n266 | 408 | 5 ms | 0.02% | 0.72% |
The error rate refers to two-qubit gate error, and the stretch indicates the increase in execution time due to inserted waiting cycles. Just as the "31.5 million" figure was a cycle count, the press release's "minimum 0.02%" likewise reflects the most favorable of the three circuit conditions: 408 logical qubits, a 5 ms cycle time, and a 0.01% error rate. By contrast, the MIPT circuit, with its 1 ms cycle time, shows an 11.53% stretch at an error rate of 0.05%. The paper's own abstract summarizes results as a range—under 0.3% at an error rate of 0.01%, and under 12% at 0.05%. Given that under unfavorable conditions computation time extends by more than 10%, the characterization of "not delaying" applies only to a portion of the table.
Vertical comparisons within the table are not made under matched conditions. Only the 408-logical-qubit circuit was evaluated with a 5 ms cycle, while the two 102-logical-qubit circuits were measured at 1 ms. Given this fivefold difference in the time available for decoding, one cannot conclude from this table that "larger scale means smaller stretch."
The press release further states that it confirmed the classical hardware load need not grow exponentially. What the paper actually demonstrates, however, is only an empirical rule: that the required computational resources scale roughly in proportion to the number of blocks handled per core.
Why can a single laptop CPU keep up?
Most of the answer lies in how cycle length differs by qubit modality. For superconducting qubits, one cycle is roughly 1 μs—Google's Willow processor reported a measured value of 1.1 μs. To keep pace with this short cycle, Google, IBM, and Riverlane have all raced to build dedicated hardware—FPGAs, ASICs, and GPUs—competing over latencies ranging from hundreds of nanoseconds to tens of microseconds. IonQ's paper, by contrast, assumes ion-trap cycle times of 1 ms and 5 ms, treating 1 ms as a longer-term representative value and 5 ms as a near-term one. Dividing 1 ms by Willow's measured 1.1 μs yields roughly 909 times the available time for decoding, and dividing 5 ms yields roughly 4,545 times (calculated by the editors).
This comparison comes with caveats. IonQ's figures are assumed values from the paper, not cycle times measured on actual hardware. The code types also differ—Google uses the surface code, while IonQ's design uses a quantum LDPC code—so the size of the problem solved per cycle is not equivalent between the two. Even so, a time differential exceeding 900-fold leaves considerable room for general-purpose CPUs to keep up.
The measured decoding times fall within that margin. The error decoder, which continuously outputs corrections, took an average of 0.99–1.89 ms per window for the 102-logical-qubit circuits, staying under a 3 ms budget. For the 408-logical-qubit circuit, it averaged 3.51–5.97 ms against a 15 ms budget. The outcome decoder, which produces the results of logical measurements, averaged 0.26–0.45 ms per cycle (against a 1 ms budget) and 0.79–0.96 ms (against a 5 ms budget). Each of these times includes both the on-the-fly generation of the decoding error model (DEM) and the beam-search decoding itself.
The use of the 12 cores also reflects a division of labor. The paper assigns 4 cores to the outcome decoder and 8 cores to the error decoder—putting the process that outputs logical measurement results and the process that continuously produces error corrections on separate cores. The underlying Walking Cat architecture (arXiv:2604.19481, April 2026, 18 authors) is designed so that the shape of code blocks does not change during computation. By combining this simplicity with the time margin afforded by the slow cycle, the paper's simulation demonstrates that the entire computation can be handled on a general-purpose CPU.
The decoding method used also has prior groundwork. The beam-search decoder is a technique from Ye, Wecker, and Delfosse published in PRX Quantum 7, 033002 (2026); XenoSpectrum reported in January 2026 that the company had achieved up to a 17-fold reduction in logical error rate compared to BP-OSD using this method. The present paper extends that decoder from a single code block to the entire computation.
The slow cycle also has a flip side. Since one cycle is roughly 909 to 4,545 times longer than Willow's, the total execution time of a computation running the same number of cycles also lengthens by the same ratio. The reason a CPU can keep up and the reason ion-trap machines compute slowly stem from the same figures.
How this differs from real-hardware demonstrations by Google, Riverlane, and Quantinuum
Real-time decoding itself has already been demonstrated on multiple actual devices. Arranging the major published cases alongside IonQ's current paper in the same columns produces the following:
| Case | Source of Error Data | Decoder Hardware | Target and Scale | Published Time Metric |
|---|---|---|---|---|
| IonQ (arXiv:2608.25027, August 2026) | Simulation | Apple M4 Max, 12 cores | General-purpose circuit with up to 408 logical qubits | Assumed cycle time of 1–5 ms |
| Google Willow (arXiv:2408.13687, published in Nature) | Real hardware | Real-time decoder connected to actual device | Distance-5 surface code memory, up to 1 million cycles | Average latency 63 μs, cycle time 1.1 μs |
| Riverlane, Rigetti Ankaa-2 (Nature Communications, June 2026) | Real hardware | FPGA embedded in control system | 8-qubit stability experiment | Average per-round time 0.44–0.79 μs, response time 9.6 μs |
| IBM researchers (arXiv:2510.21600, October 2025) | Not specified in abstract | Relay-BP on FPGA | Memory using [[144,12,12]] gross code | Average cycle time under 1 μs (assuming circuit error rate under 3×10⁻³) |
| Quantinuum Helios (announced March 2026) | Real hardware | BP-OSD on NVIDIA GPU | Bring code | Latency and logical qubit count not disclosed in published blog |
Prior demonstrations of real-time decoding by Google, Riverlane, and Quantinuum were all conducted on actual hardware. However, their targets were memory or small-scale logical operations, whereas IonQ's current result addresses an entire general-purpose computation with hundreds of logical qubits—but without using real hardware. The decoder hardware also varies across CPU, FPGA, and GPU; Quantinuum connected a GPU to actual hardware via NVIDIA's CUDA-Q QEC and NVQLink.
The time figures cannot be directly compared side by side. Google's 63 μs is average decoding latency; Riverlane's 0.44–0.79 μs is per-round processing time, while its 9.6 μs is response time—each measuring something different. IonQ's 1–5 ms figures are of a different nature still, being values the paper assumed for the time available for decoding, not measured results.
The paper frames its own position by noting, in its review of prior work, that while decoders for memory blocks and certain logical operations have been optimized, end-to-end real-time decoding for large-scale, general-purpose quantum computation had not yet been demonstrated. Read in light of this framing, IonQ's claim of being "industry first" is limited specifically to real-time decoding of an entire general-purpose computation at the scale of hundreds of logical qubits, using a single CPU. As shown in the table, the cases of real hardware running error correction in real time are limited to three: Google, Riverlane, and Quantinuum.
Two limitations the paper itself acknowledges: can the stretch hold up with real hardware error data?
The paper itself lists two limitations. First, for sufficiently difficult windows, decoding occasionally fails to converge. Second, to run large-scale simulations, the initial preparation of magic states was replaced with stabilizer states. Regarding the latter, the paper explains that this is a simplification meant to measure decoding load rather than output fidelity. In other words, what these figures measured was whether the decoder finishes its work in time—not whether the computational results were correct.
The Quantum Insider noted that actual hardware can exhibit correlated noise and calibration drift. Error data generated from a noise model does not necessarily capture such disturbances. If error data from real hardware becomes more congested, the number of difficult windows could increase, potentially altering the stretch values shown in the table.
The assumed error rate also has some distance from reality. An error rate of 0.01% corresponds to the level associated with the 99.99% two-qubit gate fidelity IonQ reported in 2025. The paper treats this error rate as one already achieved on small-scale ion-trap devices, but whether it can be maintained on a device with 11,680 physical qubits remains unshown. IonQ announced its sixth-generation, 256-qubit Superion 256 system on September 8, with customer shipments planned for 2027. The press release positions this result as the foundation for a roadmap extending beyond 256 physical qubits, but this reflects the company's own outlook—still an order of magnitude away from the scale assumed in the paper.
In the press release, Delfosse called the verification of real-time decoding across hundreds of logical qubits and millions of logical operations a milestone, saying that running on a single CPU offers a practical path toward commercial-scale fault-tolerant computation. John Gamble, VP of Architecture, added that directly validating each component enables cost-effective scaling.
The next piece of evidence to watch for is whether error data drawn from an actual ion-trap device—one maintaining a 1–5 ms cycle and an error rate around 0.01%—produces a stretch within the paper's range when run on the same 12-core configuration. If that can be demonstrated, then the path toward commercial scale that Delfosse describes will become something measurable outside of simulation.