Kepler Computing, a semiconductor startup based in San Jose, California, emerged from seven years of stealth development on September 9, 2026, to unveil a new memory technology built specifically for AI processing. In today's AI infrastructure, dominated by large language models (LLMs), the biggest bottlenecks are no longer compute processor speed but rather memory bandwidth, capacity, power consumption, and manufacturing supply capacity. HBM (High Bandwidth Memory), the current standard-bearer, depends on cutting-edge EUV (extreme ultraviolet) lithography and complex stacked packaging, and the massive capital expenditure and long lead times these require have only deepened the bottleneck. Kepler's answer combines new materials science with 3D stacking to deliver SRAM-level power efficiency and up to 10 times the capacity of HBM, without requiring cutting-edge EUV lithography—achieved instead by retrofitting existing mature-generation fabs.
Ending Seven Years of Stealth: $468 Million and US CHIPS Act Backing Underpin Kepler's Bet
Since its founding seven years ago, Kepler Computing has continued research and development without making detailed public announcements. Its founding team is composed of experts with established track records at the frontier of advanced semiconductor physics and mass-production manufacturing. Co-founder and CEO Debo Olaosebikan holds a PhD in physics from Cornell University, where he studied silicon lasers and spintronics. He previously co-founded the software development platform Gigster and served on the US Department of Commerce's Industry Advisory Committee (IAC).
Co-founder and CTO Sasi Manipatruni is the former founding director of Intel's advanced research organization, the FEINMAN Center, and is known as a co-inventor of MESO (Magneto-Electric Spin-Orbit) devices, once touted as a next-generation logic technology. The company's Chief Science Officer is Ramesh Ramamoorthy, recognized for solving the long-standing problem of fatigue in ferroelectric materials. Rounding out the leadership team are Rajeev Dokania, who led the definition of Intel's Foveros 3D stacking technology; Lars Heineck, who led mass production of seven generations of DRAM and 232-layer 3D NAND; Noriyuki Sato, who achieved FinFET integration of ferroelectric materials; and Antun Domic, a pioneer in EDA, IEEE Robert N. Noyce Medal recipient, and former CTO of Synopsys.
Both industry and government have backed this leadership team with substantial funding. Private fundraising has totaled $468 million to date, with investors including foundry giant GlobalFoundries (which directly invested $50 million), Intel Capital, AMD Ventures, UK asset manager Baillie Gifford, and Bill Gates' investment fund Gates Frontier.
Public support is also in place. In July 2026, the US Department of Commerce signed a letter of intent (LOI) under the US CHIPS Act to provide the company with up to $245 million in funding. Under this scheme, the US government would take a non-controlling equity stake, underscoring expectations for the technology as a strategic solution to AI infrastructure's memory bottleneck. The company has already processed roughly 2,000 test wafers and collected initial electrical characterization data.
Bypassing EUV: Converting a 28nm Fab Into a Memory Plant in Eight Months
In today's AI accelerator market, memory supply is dominated by HBM3E and next-generation HBM4. But manufacturing these cutting-edge DRAM chips requires massive fabs equipped with multiple EUV lithography systems from the Netherlands' ASML. Multi-layer stacking via through-silicon vias (TSVs) and advanced packaging processes are also essential, meaning a single new fab requires tens of billions of dollars in investment and two to three years to build. Delays in lithography equipment delivery and yield fluctuations have repeatedly translated directly into shipment delays for AI accelerators overall.
Kepler's approach overturns the premise of this capital expenditure arms race. The company has eliminated all dependence on cutting-edge EUV lithography, instead choosing to manufacture memory by retrofitting existing 28nm logic production lines owned by GlobalFoundries. The fab conversion is estimated to take about eight months—dramatically shorter than the two to three years needed to build a new fab, or even a typical production line conversion.
CEO Olaosebikan describes this strategy as "maximizing intelligence density per fab, and the number of fabs per dollar spent." The 28nm process is a mature manufacturing generation once used for processors predating AMD's Ryzen line, and established production assets exist worldwide at this node. By leveraging already-depreciated cleanrooms and production lines, the company can ramp up mass production quickly while minimizing capital expenditure.
| Metric / Characteristic | SRAM (on-chip cache) | HBM3E / HBM4 (current standard) | Kepler Ferroelectric Memory (development target) |
|---|---|---|---|
| Primary storage mechanism | Transistor circuit (6T-SRAM) | Capacitor charge storage (DRAM) | Ferroelectric spontaneous polarization switching (FeRAM) |
| Volatility / refresh | Volatile (no refresh needed) | Volatile (millisecond-scale refresh required) | Non-volatile (no refresh needed) |
| Lithography required | Cutting-edge logic (3nm / 2nm) | Cutting-edge EUV lithography (10nm-class DRAM) | Mature node (existing equipment such as 28nm) |
| New fab / retrofit timeline | Years to build new fab | 2-3 years to build new memory fab | ~8 months to retrofit existing fab |
| Bandwidth per watt | Extremely high (efficiency benchmark) | Medium-to-high (high refresh and wiring power) | Aims to approach SRAM-level efficiency |
| Storage capacity density | Very small (limited to a few hundred MB) | Large capacity (tens of GB/stack) | Up to 10x SRAM and HBM |
| Primary optimization target | On-processor compute cache | High-bandwidth main memory for AI training and inference | High-throughput, low-latency AI inference |
As the comparison table above shows, Kepler's technology aims to capture both the high efficiency of SRAM and the large capacity of HBM simultaneously, through a low-cost manufacturing process based on retrofitting mature nodes.
Why Ferroelectrics and 3D Stacking? SRAM-Level Efficiency, 10x HBM Capacity
At the core of the technology is a combination of ferroelectric memory (FeRAM) materials and proprietary 3D stacking. When an external voltage is applied to a ferroelectric material, the electric dipoles within its crystal structure align in a given direction, and this alignment—known as spontaneous polarization—persists even after the voltage is removed. By mapping the direction of this polarization to "0" and "1," the material functions as non-volatile memory that retains data even when power is cut.
Conventional DRAM stores charge in tiny capacitors, and as the process shrinks, charge leakage increases, requiring repeated refresh operations to recharge data on a millisecond timescale. This refresh activity, along with the charging and discharging involved in reading and writing data, has generated non-trivial power and heat losses in AI data centers. SRAM, meanwhile, requires no refresh and operates at high speed, but each bit requires six transistors, consuming large amounts of chip area and making gigabyte-scale capacity on a single chip physically difficult to achieve.
Kepler has developed proprietary composite ferroelectric materials, including hafnium oxide-based compounds, achieving precise atomic-layer deposition and crystal structure control. According to the company, combining this new materials technology with vertical 3D integration achieves "bandwidth per watt approaching SRAM levels" while delivering "up to 10 times the capacity of SRAM and current HBM."
Because no power is consumed to retain data, standby power can be significantly reduced, and the energy required for polarization switching is extremely small. This makes it possible to place model parameters—frequently accessed during large language model inference—and KV caches that retain conversation history close to the processor, in large capacity and at low power consumption.
The company also outlines a longer-term "two-act" development strategy. In the first act, it will tackle the AI memory bottleneck. In the second act, it aims to push ferroelectric switching characteristics to their limit and pursue Beyond-CMOS logic devices that could replace silicon CMOS transistors entirely.
The Road to 2027 Singapore Mass Production: Durability and Yield Will Decide the Outcome
Kepler has published a phased execution timeline for mass production. The company will begin shipping initial chip samples by the end of 2026. In 2027, it plans to ramp up mass production at GlobalFoundries' Singapore facility (a 300mm wafer fab), and production allocation for 2027 has already been finalized. The company then plans to scale production at a US-based GlobalFoundries manufacturing facility in 2028, with allocation adjustments for the 2028-2030 period currently underway.
However, physical challenges remain to be validated before memory built on new materials can reach practical deployment. Historically, the biggest reason FeRAM technology failed to gain widespread adoption as primary memory in consumer devices was "fatigue"—a phenomenon in which repeated switching makes polarization reversal increasingly difficult—along with declining reliability as the process shrinks. While the company claims to have overcome this challenge through materials science breakthroughs, whether uniform switching characteristics and sufficient commercial yield can be maintained when processing thousands to tens of thousands of 300mm wafers remains to be proven through future mass-production validation.
The interconnect interface with GPUs and various AI accelerators is another critical practical question. Whether the memory connects to processors at ultra-high density in parallel via a silicon interposer, as HBM does, or through high-speed buses such as PCIe or CXL, will significantly affect overall system throughput and thermal design. Adoption will hinge on whether the company can present a connectivity standard accepted across the ecosystem, including support from accelerator-side memory controllers and software stacks.
As memory supply shortages and rising procurement costs squeeze the return on investment for AI data centers, Kepler's attempt to achieve large capacity and high efficiency through mature-node retrofits challenges conventional thinking about capital expenditure in the semiconductor industry. The measured specifications revealed with sample shipments at the end of 2026, and the mass-production launch planned for Singapore in 2027, will serve as the first benchmarks for whether this technology can seize control of next-generation AI infrastructure.