Just 13 years after Samsung commercialized 24-layer V-NAND in 2013, the industry has reached 332 layers—and even surpassed 400 layers. As the race for layer count intensifies, a question has begun to surface: does stacking more layers really translate into higher density? In August 2026, Kioxia and Sandisk offered an answer to that question.
The "Areal Density" Metric That the Layer-Count Race Has Overlooked
When discussing 3D NAND performance, manufacturers tend to foreground "how many layers" they've stacked. Layer count is an easily understood metric and a symbol of technical prowess. But what data center operators ultimately care about is how many bits of data can be extracted from a single silicon wafer—in other words, areal density (Gb/mm²).
Layer count and areal density are not proportional. That's because density is determined by three variables: how many bits are recorded in a single memory cell (3 bits for TLC, 4 bits for QLC), how tightly cells can be packed in the lateral direction (lateral scaling), and where peripheral circuitry is placed.
Samsung's 10th-generation V-NAND (V10) boasts over 400 layers, but because it uses a TLC (3 bits/cell) structure, its areal density stops at 28 Gb/mm². Kioxia and Sandisk's BiCS10 QLC, on the other hand, has only 332 layers, yet by combining 4 bits/cell recording with lateral miniaturization, it reached 37 Gb/mm². Despite having 20% fewer layers, it wins on density by 30%. Below, we examine the mechanism behind this reversal.
The CBA Technology That Enabled a "Density Over Layer Count" Strategy
Supporting BiCS10's density gains is the CBA (CMOS directly Bonded to Array) architecture, which Kioxia and Sandisk introduced starting with the 8th generation. In conventional 3D NAND, the memory cell array and its driving circuitry (decoders, sense amplifiers, voltage generators, etc.) were formed on the same wafer. CBA manufactures these two components on separate wafers and joins them together through high-precision wafer-to-wafer bonding.
This allows each wafer to be fabricated under its own optimal process conditions. The memory array side can focus purely on stacking, while the CMOS circuitry side achieves higher performance using an advanced logic process. In the 10th generation, the number of layers in the memory array increased by 52%, from 218 layers in the 8th generation to 332 layers, while the cell pitch in the lateral direction was also optimized simultaneously. The result: 29 Gb/mm² for the TLC version (a 59% increase over the 8th generation) and 37 Gb/mm² for the QLC version (up to a 60% increase over the 8th generation).
The reason QLC achieves roughly 28% higher density than TLC is that the number of bits recorded per cell increases from 3 to 4, allowing 33% more data to be extracted from the same cell array. However, QLC requires 16 voltage levels per cell (compared to 8 for TLC), which places stricter demands on noise tolerance and durability. Reaching 37 Gb/mm² while carrying this trade-off is what gives this announcement its technical significance.
Toggle DDR6.0 and PI-LTT Achieve Both Higher Speed and Lower Power Consumption
Density alone cannot satisfy data center requirements. AI training and inference workloads constantly demand read bandwidth from storage. BiCS10 raised the NAND interface speed by 33%, from 3.6 Gb/s in the 8th generation to 4.8 Gb/s. This is the result of compliance with Toggle DDR6.0, an industry-standard specification for NAND flash, and the adoption of the SCA (Separate Command Address) protocol.
SCA is a mechanism that transfers command signals and address signals via separate paths. By splitting what was previously a shared path, it reduces command processing latency and increases the time available for data transfer. This is said to be the first time a QLC-structured 3D NAND flash has reached 4.8 Gb/s in the industry.
Higher speed typically comes at the cost of increased power consumption, since faster interfaces require output drivers to consume more power. Here, Kioxia and Sandisk deployed a technology called PI-LTT (Power-Isolated Low-Tapped Termination). This is a termination technology that suppresses output driver power consumption while maintaining signal quality, reducing power consumption by 34% during data output and 10% during input. Achieving both higher speed and lower power consumption simultaneously has direct implications for the power and cooling cost challenges facing AI data centers.
| Item | 8th-Gen BiCS8 QLC | 10th-Gen BiCS10 QLC | Samsung V10 TLC |
|---|---|---|---|
| Layer Count | 218 layers | 332 layers | Over 400 layers |
| Areal Density | Approx. 22.9 Gb/mm² | 37 Gb/mm² | 28 Gb/mm² |
| Cell Structure | QLC (4 bit/cell) | QLC (4 bit/cell) | TLC (3 bit/cell) |
| Interface Speed | 3.6 Gb/s | 4.8 Gb/s | 5.6 Gb/s |
| Input Power Reduction | Baseline | 10% reduction | Not disclosed |
| Output Power Reduction | Baseline | 34% reduction | Not disclosed |
QLC Is Reshaping the AI Data Center Storage Hierarchy
QLC NAND records 4 bits per cell, giving it 33% higher capacity density than TLC, but at the cost of lower rewrite endurance compared to TLC. While endurance constraints are a concern for consumer SSDs, AI workloads in data centers have a different character. An analysis published by Meta's engineering team in March 2025 confirmed that QLC SSDs have read bandwidth more than 4 times that of write bandwidth, making them well-suited to read-heavy workloads. Loading AI training data and inference models is precisely this kind of read-centric pattern.
QLC SSDs are forming a new tier positioned between HDDs and TLC SSDs. According to Solidigm data, QLC SSDs achieve up to an 18x reduction in footprint and 25x faster access compared to HDD arrays. BiCS10 QLC's density of 37 Gb/mm² further boosts the economics of this tier. Because more bits can be extracted from the same wafer area, cost per bit decreases, strengthening the price competitiveness of high-capacity SSDs.
Hideshi Miyajima, Kioxia's Chief Technology Officer, stated in the press release: "AI applications are expanding from generative AI to agent-based and physical AI, making data usage increasingly diverse and sophisticated. QLC technology efficiently stores the rapidly growing volume of data, providing higher performance and scalability for AI systems."
Alper Ilkbahar, Sandisk's Chief Technology Officer, also commented: "By redefining the limits of QLC NAND performance and efficiency, we've simultaneously improved density, bandwidth, and energy efficiency," positioning the technology as an expanded foundation for next-generation infrastructure.
Questions Remaining About Mass Production Transition and Consumer Rollout
The TLC version of BiCS10 began sample shipments in July 2026. With a capacity of 1Tb and a density of 29 Gb/mm² or higher, it is intended for integration into enterprise and data center SSDs. Meanwhile, the QLC version announced this time is based on the same 332-layer process as the TLC version. Chip capacity has not been disclosed, but assuming the same die size and cell count as the TLC version's 1Tb, switching to 4 bits/cell would theoretically yield 1.33 Tb. However, this is speculation, and Kioxia and Sandisk have not released official figures.
A more significant uncertainty concerns yield and mass production timing. QLC requires finer distinction between voltage levels than TLC, making yield harder to secure. Both companies explain that once yield reaches target levels, they can achieve "lower cost than competing high-density QLC ICs," but they have not disclosed when that condition will be met.
Samsung's trajectory is also becoming more uncertain. The V10 boasts over 400 layers and an interface speed of 5.6 Gb/s, but while mass production is planned to begin in the second half of 2026, full-scale purchase orders had not been confirmed as of May of that year. Samsung has also begun prototyping the V11 (500-layer class), and the layer-count race continues. While there are industry-wide projections of reaching 1,000 layers by 2030, the practical metrics of density over layer count, and cost per bit over density, are increasingly moving to the center of evaluation.
BiCS10 QLC's target is limited to data center SSDs, with no mention of expansion into consumer client SSDs. Challenges in QLC write endurance and controller design remain barriers preventing its application to mobile devices and PCs. How much rack space the figure of 37 Gb/mm² can actually save remains an answer that awaits progress in post-mass-production yield and SSD commercialization.