MediaTek is strengthening its advanced packaging workforce, a factor that will determine the success or failure of its AI data center ASICs. On August 31, former TSMC executive Chris Hou—now MediaTek's Vice President of Advanced Packaging—said his first priority would be urgent reinforcement of this area, along with continued hiring. A review of the company's open job postings shows that MediaTek isn't simply looking for one expert well-versed in packaging technology. Rather, it's building an organization that connects 3DIC design methodology all the way through substrate procurement, enabling mass production of massive AI ASICs exactly as designed.
What Chris Hou's Comment Reveals About the Integration Burden on Fabless Companies
Chris Hou left TSMC in June 2026 after roughly 30 years at the company, during which he worked on TSV, chip stacking, 2.5D CoWoS, and silicon photonics development. According to UDN, he also coined the name for TSMC's optical-electrical convergence platform, COUPE. After joining MediaTek, he appeared at the International Forum on Silicon Photonics at SEMICON Taiwan 2026, where he described the current state of advanced packaging as requiring "urgent reinforcement."
This comment doesn't mean MediaTek lacked packaging technology altogether. The company already touts experience with large-scale packages using CoWoS and InFO, and is advancing 2.5D, 3D, and 3.5D designs for AI data centers. But the boundaries of the work differ between smartphone SoCs and AI ASICs that carry multiple compute dies and HBM. For the latter, an approach where packaging methods are decided only after logic design is finished simply won't work in time.
Fabless companies promise customers performance, power consumption, and delivery schedules without owning manufacturing facilities themselves. To keep those promises, they must understand the options presented by foundries and assembly houses, and lock in package architecture early in the design process. Power, thermal, and signal verification must also span both chip and package. The talent shortage Chris Hou referred to isn't the kind of shortage that outsourcing manufacturing can solve.
Six Open Positions Cover Everything From Design to Mass Production and Procurement
As of September 1, 2026, six confirmed MediaTek job postings span six functions: 3DIC design methodology and sign-off, substrate and RDL layout, 3.5D design integration, new product introduction and mass production, reliability and supplier quality, and substrate procurement with long-term capacity assurance.
| Job Posting | Primary Responsibilities | Role in AI ASIC Production |
|---|---|---|
| 3DIC Advance Package Design Engineer | 2.5D/3D design methodology, final physical/electrical/thermal verification | Guides chip and package design completion under unified standards |
| Senior Substrate Layout Engineer | CoWoS-S/L/R, EMIB RDL and substrate routing and physical verification | Establishes viable signal and power routing paths on large substrates |
| Technology Engineer (3.5D methodology) | Design methodology from RTL to GDS through packaging | Connects logic design with thermal and power design at an early stage |
| Senior Advanced Packaging Engineer | 2.5D/3.5D, heterogeneous integration, new product introduction, mass production | Moves prototypes through process qualification into mass production |
| Package Technology Reliability Engineer | Risk assessment for 2.5D/3D/CPO, substrate analysis, supplier qualification | Reduces failures and quality incidents in large packages before mass production |
| IC Substrate Sourcer | Long-term ABF substrate capacity, upstream materials, cost, manufacturability | Prevents situations where a completed design cannot be manufactured |
What this table reveals is that hiring isn't confined to R&D functions. Alongside engineers who build design flows sit engineers who move prototypes into mass production. Procurement staff tracking substrate supply allocation and raw materials round out the team. Even if design-stage performance targets are met, a product won't materialize if substrates can't be secured or if warpage and heat after assembly hurt yield. MediaTek appears to be building an internal structure that proactively eliminates a chain of failure points, rather than scattering responsibility across separate external partners.
That said, the job postings don't specify headcount or organizational launch timing. The six current listings shouldn't be read as six new hires or as net growth for 2026. What can be confirmed is simply that MediaTek is currently recruiting experienced professionals capable of connecting design through mass production while also managing quality and supply.
At the 10,000–20,000 Square Millimeter Scale, This Is No Longer Just Back-End Work
In its official explanations for AI data center products, MediaTek states that in 2.5D packaging, compute dies and HBM are placed side by side on a silicon interposer, keeping total area under 10,000 square millimeters. In 3.5D packaging, vertical stacking is added to integrate CPU, XPU, HBM, and I/O chiplets into a 10,000–20,000 square millimeter footprint. A separate official page also outlines a roadmap toward even larger packages of roughly 8–9 reticles.
As package area grows, packaging shifts from being a container that holds components to becoming the foundation of system-level design. Connecting to HBM at wide bandwidth requires securing interposer and redistribution layer routing paths in advance. Clustering high-power compute dies increases voltage drop and heat generation. In generations that use CPO, components converting electrical signals to optical signals and their control dies also become part of the same design scope.
TSMC's 2025 annual report explains that CoWoS integrates multiple SoCs and HBM into a single package. CoWoS-L products, which use large reticles, are expected to begin mass production in 2026. COUPE stacks electrical control dies with silicon photonics dies and targets 2026 for CPO-oriented mass production. These are TSMC's own technology plans and don't guarantee adoption in MediaTek products. Even so, the reason MediaTek needs Chris Hou's experience is clear: optimizing design rules, thermal management, power delivery, and optical-electrical convergence separately won't add up to a viable massive package as a whole.
Even With CoWoS and EMIB-T as Options, Integration Responsibility Remains
On its official ASIC pages, MediaTek lists TSMC's CoWoS-S/R/L alongside Intel's EMIB-T, SoIC, and Foveros as supported technologies. Having multiple manufacturing paths makes it easier for customers to choose packaging based on performance, cost, and available supply capacity. But more options also mean more work on the design side.
CoWoS integrates dies and HBM on a large interposer. EMIB-T connects adjacent dies using a silicon bridge embedded in the substrate. Different architectures mean different wire lengths, power delivery, heat dissipation paths, substrate materials, and verification procedures. The same logic design can't simply be transplanted mechanically between two different packaging schemes. This is exactly why MediaTek's job postings line up design methodology, substrate layout, material selection with suppliers, and mass-production feasibility checks side by side.
What a fabless company needs to hold in-house here isn't the operational skill to run assembly equipment. It's the ability to determine required HBM bandwidth and I/O from customer workloads, select the packaging approach, and push through final physical, electrical, and thermal verification. After prototyping, the company must assess yield and reliability while securing substrate and assembly supply capacity. Even though manufacturing itself can be outsourced, the responsibility for judging under what conditions mass production is viable stays with MediaTek.
Hiring Success Will Be Measured by Mass Production and Customer Outcomes
In June, MediaTek said it had raised its 2026 AI data center ASIC revenue outlook to $2 billion. As the dollar figure grows, packaging failures shift from being technical problems to business problems. Delayed design changes push back tape-out and the start of mass production, forcing companies to re-secure substrate and assembly supply capacity. If yield doesn't improve, the cost and delivery timelines promised to customers also fall apart.
Hiring Chris Hou and expanding job postings confirms that MediaTek recognizes this risk. But the size of the team, the division of roles by customer, and which packaging approach ongoing products will use haven't been disclosed. It would be premature to equate the number of job listings with competitive strength.
The real results will show up not in the titles of new hires, but in how customer projects actually progress: whether 3DIC sign-off can be completed early in the design process, whether large substrates can be secured, and whether yield and reliability can be sustained from prototype through mass production. If MediaTek can move all of these on the same schedule, it will have transformed advanced packaging from a procured commodity into genuine execution capability for its AI ASIC business.