According to on-site reporting by Tom's Hardware, Micron explained at the Hot Chips 2026 semiconductor technology conference on August 23, 2026, that the problem of HBM consuming more wafer capacity than DDR5 of the same capacity and process node worsens with each generation. The current benchmark, based on HBM3E, is roughly 3x, and closing that gap without sacrificing performance is difficult. The more bandwidth AI accelerators demand, the more circuitry and manufacturing steps balloon beyond what's needed for capacity alone. HBM's growth boosts AI server performance, but it simultaneously reduces the number of bits the DRAM industry can supply from the same wafer.
This "3x" figure refers neither to price differences between finished products nor to differences in package volume—it's the ratio of wafer supply required to manufacture the same capacity at the same process node. Micron's March 2026 earnings materials also explicitly stated that HBM demand comes with a 3-to-1 input ratio relative to DDR5, and that this ratio will rise further in future HBM generations. Tom's Hardware reported that company executives explained during Q&A that as long as bandwidth-prioritized designs continue, this gap will not narrow.
"3x" Is a Wafer Input Ratio, Not a Price Comparison
The roughly 3x comparison applies when manufacturing the same number of bits in HBM3E versus DDR5. In past investor materials, Micron has explained that at the same process node, HBM3E consumes approximately 3 times the wafer supply of DDR5. Even if a wafer is allocated to HBM production, it doesn't yield the same amount of memory bits as it would producing DDR5. As HBM's share rises, downward pressure on the total bits the industry can ship increases—even if DRAM fab wafer input volumes remain unchanged.
HBM stacks DRAM dies vertically to achieve high bandwidth, connecting each layer through TSVs (through-silicon vias). According to Micron's manufacturing explanation, HBM4 requires separately manufacturing DRAM dies with TSVs, a top-layer die without TSVs, and a logic die that connects to the system. Dies that pass testing are selected for stacking, and the completed stack is inspected again. This involves more steps than DDR5, which is laid out flat, and area must also be allocated for TSVs and connection circuitry.
However, the 3-to-1 ratio cannot be directly translated into retail pricing. Memory prices are driven not only by demand and inventory but also by the timing of new fab startups and the product mix manufacturers choose. Allocation toward HBM can be one factor constraining supply, but attributing DDR5 price increases to a single cause would be an overreach.
256 Banks Push Up Both Bandwidth and Die Area
In presentation materials from the Hot Chips talk covered by Tom's Hardware, a design example showed HBM4 DRAM dies with 256 banks compared to DDR5's 32 banks. A bank is a section that can access data independently; operating many in parallel increases the amount of data that can be moved at once. In exchange, the circuitry for data paths and power delivery expands, and TSVs are also required to pass through the stacked dies. The very mechanism used to boost bandwidth pushes up die area.
There's also a significant gap in bandwidth per die. The same materials compared HBM3E at 256GB/s against DDR5 at roughly 8GB/s. Rather than relying on a small number of high-speed signal lines like DDR5, HBM flows large volumes of signals in parallel through a wide interface. Increasing pin speed, bank count, and interface width all boost bandwidth—but this runs counter to reducing circuit area per unit of capacity.
According to Tom's Hardware's coverage of the talk, Micron's Raghu Sreeramaneni explained that while computing performance triples roughly every two years, HBM bandwidth growth has been less than doubling. Because computing capability advances faster, the "memory wall"—where processors wait on data from memory—persists. Even as HBM gets faster, it fails to keep pace with growing demand, requiring designs that push bandwidth even higher. In his view, this cycle widens the area gap with DDR5 with each generation.
HBM4 Boosts Bandwidth 2.3x at the Same 36GB Capacity
Micron's production version of HBM4 operates 2,048 I/Os at over 11Gbps, delivering more than 2.8TB/s of bandwidth per stack. The capacity and stack count—36GB across 12 layers—match the company's HBM3E 12-layer product, but bandwidth increased 2.3x. This is a generational update that raises interface width and transfer speed without increasing capacity.
Micron states it began mass shipments of this 36GB product in Q1 2026, designed for NVIDIA's Vera Rubin platform. It's a generational upgrade that keeps capacity flat while boosting the speed at which data reaches the GPU. However, Micron has not disclosed the precise wafer input ratio between HBM4 and DDR5. The 2.3x bandwidth figure represents the product's targeted performance—it is not a number indicating the increase in silicon usage.
In a two-GPU schematic example presented by Tom's Hardware, memory occupied roughly 90% of the silicon area within the package, reaching about 8 times the area of the GPU die itself. However, this illustrates one specific configuration and is not a ratio that applies to all GPU packages. Sreeramaneni explained that if even one DRAM die has a defect or reliability issue, it affects the reliability of the entire system-in-package.
Rising Layer Counts Create Thermal and Supply Constraints
The next lever for increasing capacity is stacking even more dies. Micron is sampling a 48GB, 16-layer HBM4 product to customers, increasing per-stack capacity by 33% over the 36GB, 12-layer version. According to Tom's Hardware, Sreeramaneni said at Hot Chips that a path exists up to 16 layers, while acknowledging that stacking beyond that still requires substantial further development.
As layer counts increase, the path for heat to escape lengthens. Per Sreeramaneni's explanation as reported by Tom's Hardware, the logic die handling the high-speed interface sits at the bottom of the stack, while the heatsink is placed on top. As more DRAM layers are added in between, thermal resistance rises. Even as process shrinks make dies smaller, the input ratio per unit of capacity won't improve unless thermal design, TSV and bonding, and post-sorting yield can all be solved simultaneously.
The exact increase in silicon consumption for HBM4 versus DDR5 has not been disclosed. The roughly 3x figure is based on HBM3E, and at this stage only the direction—that the gap widens with each generation—has been indicated. Judging future supply and demand will require watching how far each company can actually improve wafer input ratios and yield rates. Whether HBM's bandwidth expansion and general DRAM supply can coexist will become clear once 16-layer products ramp at production yields and new fab capacity comes online.