A CXL 3.2-compliant controller that expands server memory beyond the CPU has entered trial production. Chinese semiconductor design company Montage Technology (澜起科技) announced on July 30, 2026, the trial production of its memory expansion controller (MXC), the "M88MX6852." The company describes it as an industry first.
What matters in this announcement is less the headline figures—up to 64 GT/s and DDR5-8000—and more how far the product has progressed toward commercialization. The same model number began sampling to key customers as a CXL 3.1-compliant part back in September 2025. This time, Samsung Electronics and SK hynix have incorporated it into their next-generation CXL products and completed initial validation. What matters here is that trial production and initial validation on the memory maker side have come together. However, Montage has not disclosed the scale or yield of trial production, nor the timing of supply start to customers.
A single chip bridging 64 GT/s CXL and DDR5-8000
The M88MX6852 is a CXL Type 3 controller that sits between the host CPU and external DRAM. It converts host memory requests arriving via CXL.mem into DDR commands, while handling device discovery, configuration, and management through CXL.io. It integrates a CXL controller, two DDR5 memory controllers, a PCIe 6.2 PHY, a DDR5 PHY, and a RISC-V subsystem into a single chip.
On the host side, it can operate as an x8 link at up to 64 GT/s, and can also be split into two x4 ports. On the memory side, it supports DDR5-8000 UDIMM, RDIMM, and on-board DRAM. The intended form factors are PCIe add-in cards and EDSFF memory modules.
Here, 64 GT/s and 8000 MT/s measure different things. The former refers to the number of transfers per second on each lane of the PCIe 6.2 physical layer, while the latter refers to the transfer rate of the DDR5 interface. Neither figure directly translates into effective GB/s, nor do they indicate system-level performance, which includes CXL protocol overhead, memory configuration, and access patterns. Montage has not disclosed effective bandwidth, total latency, or power consumption.
Being able to increase external capacity is also not the same as being able to use it at the same speed as local DRAM. Requests to CXL-attached memory pass through the host link and the MXC. Whether the resulting latency impact can be mitigated depends on the precision of tiering—keeping frequently accessed pages in CPU-attached memory while placing capacity-prioritized data on the CXL side. Maximum supported capacity has also not been disclosed, and 64 GT/s alone cannot determine a system's superiority.
How far has the same M88MX6852 progressed in roughly 11 months?
The CXL 3.1 version from September 2025 and this CXL 3.2 version share the same model number, as well as their key performance characteristics: a 64 GT/s x8 link and DDR5-8000 support. In other words, it would not be accurate to characterize what's new this time as simply an increase in interface speed. The substantive change is the shift from customer sampling to trial production, and Samsung and SK hynix completing initial validation on the module side.
The hardware differences from the previous generation are clear. According to Montage's product listings, the CXL 2.0-generation M88MX5891/5851 supported an x8 link at up to 32 GT/s over PCIe 5.0, and worked with both DDR4 and DDR5. The M88MX6852 doubles the link transfer rate to 64 GT/s per lane over PCIe 6.2, while narrowing memory support to DDR5 only. The package has also changed, from the previous generation's 767-ball or 716-ball FCCSP to a 1211-ball FCBGA.
The new chip also comes with an SDK, analysis tools, and test tools. Montage anticipates interoperability with major server platforms including Intel Xeon and AMD EPYC, but what the announcement confirms is limited to initial validation by memory makers. This needs to be distinguished from formal listing on the CXL Consortium's compliance list or certification with specific CPUs.
CXL 3.2's real focus is memory operations, not speed
CXL 3.2 was published on December 3, 2024. The 64 GT/s physical layer was already introduced in the CXL 3.0 generation. Version 3.2 refines mechanisms for monitoring and maintaining memory devices, strengthens OS integration, and expands security.
A representative example is the CXL Hot-Page Monitoring Unit (CHMU). It monitors memory page access frequency using a standardized method, making it easier to move frequently used data to faster memory and less-accessed data to capacity-oriented tiers. CHMU itself does not move pages; rather, it provides the OS or management software with the information needed to make placement decisions. The CXL Consortium has explained that the goal is to enable OS-level memory tiering implementation without requiring individual applications to be recompiled.
On the maintenance side, the standard unifies event logging formats and adds the ability to switch firmware during operation. It also extends Post Package Repair and performance monitoring events. Enhancements to the Trusted Security Protocol (TSP) and IDE protection help establish trust boundaries for scenarios where multiple hosts or virtual machines share external memory.
However, according to the CXL Consortium, there is no mechanism by which hardware registers a version number to identify itself as a "CXL 3.2 product." Software must individually discover and use whatever features are implemented. Therefore, a "CXL 3.2-compliant" label alone does not guarantee that all optional features defined in the specification are enabled. For production systems, it remains necessary to verify which specific features are needed and to confirm interoperability test results.
After proving capacity mobility, the focus shifts to manufacturability and real-world performance
Ahead of trial production, Montage in April 2026 publicly demonstrated a Dynamic Capacity Device (DCD) built on its CXL 3.2 x8 controller. The link was split into two Gen6 x4 connections, dynamically allocating memory capacity between two hosts.
In the demonstration, Host 1's 64 GB was incrementally increased to 72 GB and then 80 GB, then released back down to 72 GB and 64 GB. Next, 8 GB was allocated from a shared pool to Host 0, expanding it from 32 GB to 40 GB. This was a functional demonstration showing that capacity could be added, returned, and reallocated to a different host without a reboot.
At the same time, this configuration cannot function with the controller alone. It combined a Fabric Manager and Orchestrator, a Linux kernel patched for DCD support, and firmware for the Multi-Head Device. Performance under load, large-scale failure recovery, and the maturity of the operational software all need to be verified separately.
The CXL 4.0 specification was published on November 18, 2025, defining 128 GT/s. Even so, trial production of a CXL 3.2 chip still carries meaning in 2026, because the process from specification publication to silicon design and manufacturing, memory module integration, and validation with hosts and OSes does not conclude all at once. When will the M88MX6852 move to mass production, and under what products will Samsung and SK hynix ship it? What comes next is not a matter of specification version numbers, but whether real systems can expand capacity while keeping latency and power consumption in check—and ultimately lower operating costs.