NAURA Technology Group (North China Huachuang), a Chinese semiconductor equipment manufacturer, has announced the development of a new etching technology capable of processing multilayer stacks of silicon (Si) and silicon-germanium (SiGe) in a single pass — a critical process step for 3D DRAM, the next-generation memory architecture currently under research worldwide. Following this announcement, some tech media outlets have run headlines framing it as "a breakthrough that lets Chinese memory giant CXMT (ChangXin Memory Technologies) bypass U.S. EUV lithography restrictions and move forward with 3D DRAM production."
That framing significantly overstates what was actually presented at the conference. What NAURA disclosed is lab-scale demonstration data for one of the most difficult elemental technologies in the vertical-stacking process — not proof of adoption by any memory maker, nor evidence of a mass-production tool in operation. It's necessary to separate what the disclosed figures actually mean from the speculation added on top by media coverage.
The Gap Between the Conference Abstract and Media Reporting
In an article dated September 4, 2026, the tech outlet Wccftech reported that NAURA had published a paper in an "IEEE journal" describing a two-step etching technology capable of uniformly processing 64-layer 3D DRAM stacks, and claimed this would free Chinese memory manufacturing from horizontal scaling constraints. However, this report contains significant misunderstandings regarding the timing of the announcement, the nature of the publication venue, and claimed partnerships.
Checking the primary source reveals that the document in question is not an academic paper published in a peer-reviewed journal. It is a proceedings paper included in the conference proceedings of CSTIC 2026 (China Semiconductor Technology International Conference 2026), held March 22–24, 2026, at the Kerry Hotel Pudong in Shanghai. The paper was added to IEEE Xplore on June 2, 2026, with document number 11537759 and DOI 10.1109/cstic68613.2026.11537759. The paper's title is "Cyclic Etching of SiGe/Si Multilayers with Fluorine Chemistry for 3D DRAM Applications."
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| NAURA's Claimed Values (Metric Value) | |
|---|---|
| Selectivity (SiGe vs. Si, x) | 500 |
| Uniformity (depth direction, %) | 95 |
| Si layer loss (at 200nm lateral etch, Å) | 10 |
As the figures above indicate, NAURA's research team claims to have achieved, in lab testing, extremely sharp control values: a selectivity exceeding 500x, uniformity above 95%, and Si layer loss of less than 10Å when etching SiGe laterally over a 200nm distance.
However, all listed author affiliations are solely NAURA (China). The authors are Yiming Ma, Guang Yang, Jiangpu Yu, and Litian Xu. Not a single co-author from an external semiconductor manufacturer — including CXMT — appears on the paper. As of September 2026, IEEE Xplore records show zero citations for this paper. Wccftech published its article on September 4, 2026 — more than five and a half months after the proceedings became public at the conference. During that entire period, there has been no evidence of any new commercialization press release or customer-acquisition announcement from NAURA.
The narrative Wccftech built — that this is "technology enabling CXMT to overcome EUV constraints" — is an inference constructed independently by the media outlet. NAURA's paper abstract contains no mention whatsoever of CXMT by name, any specific customer, or U.S. export restrictions. What actually happened is that a foundational report on an elemental technology, presented by a single equipment vendor at a technical subcommittee of an industry conference, was transformed through the media filter into a narrative about breaking through a national semiconductor blockade.
In the field of semiconductor process development, cases where the announcement of a single elemental technology directly leads to mass production of a final product are extremely rare. Particularly in the development of fine-processing equipment, numerous hurdles exist between demonstrating a process on a standalone tool and achieving integrated testing in an actual fab, yield improvement, and mass-production qualification. NAURA's announcement represents only the first step: a lab-level proof of principle.
The Chemistry Behind the 500x Selectivity Claim: Adsorption and Purging
Setting aside the hype, the process NAURA presented does directly address a genuine structural challenge in 3D DRAM.
Current planar DRAM arranges capacitors and transistors flat on a substrate, increasing capacity by scaling down to the limits of photolithography. However, as processing dimensions approach the 10nm range, physical walls emerge: interference between adjacent cells, limits on capacitor aspect ratio, and increased leakage current. The concept devised to overcome this is 3D DRAM, which stacks memory cells vertically in the manner of 3D NAND flash memory.
One approach widely regarded as mainstream for manufacturing 3D DRAM involves alternately depositing many layers of silicon (Si) and silicon-germanium (SiGe), then selectively dissolving away (etching) only the SiGe layers. Conductive or insulating films are then filled into the resulting cavities to form word lines, bit lines, and transistor gate electrodes in three dimensions.
The biggest obstacle in this process is selectivity and depth-direction uniformity. If the etching gas that dissolves SiGe also eats away at the neighboring Si layer, the thickness of the Si layer responsible for the transistor channel becomes uneven, breaking down device characteristics. In deep stacks of dozens of layers, phenomena arise where the etching gas erodes the upper layers preferentially without reaching the bottom layers, or where etching byproducts accumulate deep in the stack and inhibit reactions — a so-called micro-loading effect.
According to NAURA's paper abstract, the company developed a proprietary two-step cyclic etching method to address this challenge.
In the first step, under unbiased, field-free conditions with no substrate bias voltage applied, electrically neutral fluorine radicals are supplied into the chamber from a remote plasma with ions removed. These fluorine radicals preferentially react with the SiGe layer. During this process, volatile germanium fluoride species competitively adsorb onto the silicon surface, forming a protective layer that suppresses etching of the Si layer itself.
In the second step, a plasma-assisted purge process is carried out. The non-volatile solid reaction byproducts generated in the first step are decomposed and volatilized using plasma energy, and forcibly expelled from the bottom of the stack. Repeating this cycle prevents byproduct accumulation in deep regions of the stack.
The specific performance figures reported in the abstract are the following three:
- SiGe-to-Si etch selectivity exceeding 500:1 Wccftech's article text mistakenly reverses the subject, describing it as "Si to SiGe," but the correct interpretation is that the SiGe etch rate is more than 500 times faster than that of Si. However, the absolute etch rates for SiGe and Si that underlie this selectivity calculation are not disclosed in the abstract as confirmed.
- Si layer loss of less than 10Å (1nm) when etching SiGe laterally by 200nm Under conditions where 200nm of SiGe is removed laterally, the reduction in thickness of the Si channel layer that should remain intact is kept to 1nm or less.
- Structural depth-direction uniformity exceeding 95% across 64 layer pairs (128-layer multilayer stack) Uniformity in the depth direction across the entire stack is claimed to exceed 95%, but the actual measured design dimensions or gap widths that serve as the denominator for this ratio are not disclosed in the abstract.
Note that Wccftech's article includes a calculation example stating "if the top layer is 200nm, the bottom layer maintains a thickness of at least 190nm" — but this is merely an example the reporter calculated independently from the 95% figure, not a measured value recorded in NAURA's paper.
In the conclusion of the paper abstract, the authors state only modestly that this process "provides a manufacturable solution for defining critical structures in 3D DRAM architectures." Nowhere does it state that application to a mass-production line has been completed.
This two-step cyclic process holds potential to substantially suppress the localized over-etching and reaction byproduct accumulation that occur in conventional continuous isotropic etching. In particular, the precise introduction of fluorine radicals under field-free conditions, followed by forced byproduct exhaust via purging, is an effective means of maintaining chemical reaction uniformity in high-aspect-ratio structures. However, even if this chemical advantage is confirmed, whether it can be reconciled with the throughput and operational stability required on an actual production line is a separate question entirely.
Vertical Stacking as an Option Under EUV Restrictions
Why is this SiGe selective etching drawing attention within China's semiconductor ecosystem? The backdrop is a geopolitical blockade surrounding cutting-edge lithography equipment.
Under export restrictions imposed by the United States and its allies, shipments of Dutch ASML's EUV lithography systems to China have been completely halted. In planar scaling, Chinese fabs have chosen to substitute deep ultraviolet (DUV, 193nm-wavelength immersion ArF scanners) with multiple exposure passes (multi-patterning), replacing what EUV — at a 13.5nm exposure wavelength — could accomplish with a single exposure pass for fine patterns.
According to a 2026 report on China's memory industry by market research firm Fa Xian Gong Chang, CXMT — China's only major DRAM manufacturer — is reportedly mass-producing 1a nm-generation DRAM at its fifth-generation process (G5). However, the company's strategy relies on an approach of "substituting EUV with multi-patterning," reportedly employing quadruple exposure (SAQP) and even sextuple exposure using immersion DUV scanners. The same report predicts that CXMT's D1α generation (roughly equivalent to the 14nm node) will complete R&D in the second half of 2026, with mass production beginning in 2027.
However, DUV-based multi-patterning causes mask costs to spike and yields to decline as the number of exposure passes increases. Pushing horizontal scaling to its absolute limit is extremely difficult to sustain economically for companies without access to EUV.
This is where the 3D DRAM strategy emerges as an option: keeping planar scaling at a moderate dimension (for example, in the 20nm or 30nm range) while stacking cells vertically across many layers to boost overall bit density per chip. If vertical stacking proves viable, it becomes mathematically possible to manufacture high-capacity memory using existing DUV lithography equipment without cutting-edge EUV scanners — following the same path that allowed 3D NAND to achieve cost reductions by increasing layer counts with each generation.
Realizing 3D DRAM requires two critically important capabilities: anisotropic etching to drill high-aspect-ratio vertical holes, and isotropic selective etching to uniformly remove specific layers laterally from a multilayer film. NAURA's work addresses the latter.
But this context alone does not mean NAURA's research results directly translate into CXMT mass production. The narrative Wccftech drew — that "NAURA's etching technology allows CXMT to overcome EUV restrictions" — amounts to little more than a trial balloon that forcibly connects geopolitical context with an individual technical report.
Observing China's memory supply chain as a whole, it is true that a strong incentive exists to increase the ratio of domestically produced components. As U.S. regulatory tightening continues, a technology route that reduces dependence on lithography equipment and boosts integration density through innovations in other processes such as deposition and etching is extremely attractive to China's semiconductor industry. However, an architectural transition requires clearing a vast web of patents and elucidating entirely new device physics — it is not simple enough to be achieved through the progress of a single equipment maker alone.
Scrutinizing the Mass-Production Variables Missing from Lab Data
In semiconductor process development, a deep chasm exists between conference presentation data and the establishment of a commercial mass-production line. Careful examination of NAURA's paper abstract reveals that several critical indicators, indispensable for evaluating this as a manufacturing technology, remain undisclosed.
First, etch rate and processing throughput are entirely unknown. Even if the SiGe-to-Si selectivity exceeds 500:1, if processing a single wafer takes several hours, it cannot be deployed on a commercial mass-production line. Cyclic processes that provide atomic-layer-level precision control are often extremely slow. Unless details of the etch amount per cycle (nm/cycle) and the time required for purging are disclosed, the economic viability of this as a manufacturing tool cannot be evaluated.
Second, data on wafer-level uniformity and defect density is missing. What the abstract refers to is "depth uniformity across 64 layer pairs"; there is no mention of whether the same results were obtained across the center and edge of a full 300mm wafer. Additionally, while plasma-assisted purging is claimed to remove non-volatile byproducts, whether residual particles cause pattern collapse or shorts remains unverified.
More decisively, results integrating this with an actually functioning memory array are not shown. What NAURA processed was a blanket film (or simple test pattern) of alternating SiGe and Si layers — it was not formed into transistor gate insulators, connected to capacitors, and wired with bit lines to operate as a functioning memory cell array. In 3D DRAM, the extremely thin Si layer remaining after etching must retain mechanical strength while withstanding the high-temperature processing of subsequent steps.
The Wccftech article also shows technical confusion in places. In an apparent attempt to corroborate NAURA's results, the outlet abruptly cites a 2023 paper by Liu et al., published in the academic journal Nanomaterials (Liu, Enxu, Junjie Li, Na Zhou, et al. 2023. Nanomaterials 13(14): 2127). However, that Liu et al. study concerns "selective dry etching of a 15-cycle Si0.7Ge0.3/Si multilayer structure in a Gate-All-Around (GAA) transistor process" — an entirely separate study with a different layer count and application. The 64-layer stack for 3D DRAM and the 15-layer stack for logic-chip GAA nanosheets require vastly different orders of magnitude in aspect ratio and gas penetration depth. The two cannot be conflated.
In other reported studies on cyclic SiGe etching using nitrogen trifluoride (NF3) chemistry for GAA applications published in Nanomaterials, selectivity is reported at roughly 11 to 42, with per-side silicon loss of approximately 0.44nm to 0.52nm. While a direct comparison is not possible due to differing target structures and film thicknesses, this context illustrates just how ambitious NAURA's claimed "selectivity exceeding 500x" figure is.
Caution is also warranted from the standpoint of source reliability. While CSTIC is China's largest international semiconductor conference, with ten technical subcommittees, its proceedings papers are primarily brief technical reports spanning only a few pages, and cannot be equated with the rigorous peer review of major academic journals, which involves detailed experimental data and verification of reproducibility.
| Company / Program | Publication Venue / Source / Timing | Verification Stage | Disclosed Quantitative Metrics | Independent Verification | 3D DRAM Mass-Production Status |
|---|---|---|---|---|---|
| NAURA | CSTIC 2026 proceedings (IEEE Xplore, March 2026) | Lab demonstration (materials etching) | Selectivity >500:1, Si loss <10Å (at 200nm lateral etch), uniformity >95% (64 layer pairs) *absolute rates and dimensions undisclosed | None (in-house lab announcement only) | No commercialization or mass-production track record |
| Samsung Electronics | Joint paper with imec, KU Leuven, Lam Research (2026) | Device simulation | Characteristics of stacked structures using oxide semiconductor channels | Co-authored by joint research institutions | Not commercialized (industry observers estimate 2028 or later) |
| SK hynix | Design engineer hiring at U.S. subsidiary (reported July 2026) | Design development, early-stage partnership | No quantitative values disclosed (joint development with U.S. customer) | None (job postings/media reports) | Not commercialized |
| Applied Materials | Patent application publication (published March 2026) | Patent filing (structure/method) | High-aspect-ratio SiGe/Si selective etch structure | None (IP filing) | Elemental patent as an equipment supplier |
As the comparison table above makes clear, efforts toward commercializing 3D DRAM are being pursued by major players worldwide through diverse approaches, but all remain confined to the stages of basic research, patent filings, or simulation. While NAURA's published figures show a strikingly high selectivity, in terms of full-device integration verification, the company remains at an early stage — similar to its competitors.
The Race Among Global Giants and the Patent Battlefield
The development race surrounding 3D DRAM is not the exclusive domain of Chinese companies. In fact, this is a field where the world's top three memory makers — Samsung Electronics, SK hynix, and Micron Technology — along with major U.S. equipment makers such as Applied Materials and Lam Research, are leading the basic research.
According to a report by Taiwanese research firm TrendForce, citing South Korean outlet Newspim, Samsung Electronics has published a paper on a monolithic 3D DRAM architecture using oxide semiconductor channels (such as IGZO), in collaboration with the Belgian international research institute imec, KU Leuven, and U.S.-based Lam Research. This achievement also remains at the simulation stage, with no specific commercialization timeline disclosed. Some industry reports project that Samsung will complete development of 10A nm-generation DRAM in 2026, conduct quality testing in 2027, and begin mass production in 2028 or later — but these are external analyst estimates, not official commitments from the company.
Meanwhile, according to a TrendForce report citing ZDNet, SK hynix has begun hiring design engineers for "3D-Stacked DRAM-on-Logic" through its subsidiary in San Jose, California. This is seen as the formation of a dedicated team to advance joint development with a specific U.S. customer, but it also indicates that the effort remains in the design and early-architecture exploration stage.
Looking at manufacturing equipment patent trends, U.S.-based Applied Materials has filed extremely important patents related to 3D DRAM structures. According to patent database PatSnap, the company published a patent on March 17, 2026, covering a structure that uses heteroepitaxial multilayers of single-crystal silicon (c-Si) and single-crystal silicon-germanium (c-SiGe), forms high-aspect-ratio holes, and then selectively etches away the SiGe.
The method itself — alternately stacking SiGe and Si multilayers and creating cavities through selective etching — is a well-known approach that equipment makers and research institutions worldwide are already competing intensely to perfect. While NAURA's disclosure of basic data for a deep 64-layer-pair stack in this competitive field represents genuine technical progress, the company has not obtained a uniquely dominant technology that sets it apart. At present, no semiconductor manufacturer anywhere in the world has reached commercial mass production of 3D DRAM; the entire industry remains in a phase of trial and error involving prototypes and simulations.
Multiple structural variations are being explored across companies for 3D DRAM, including horizontal-channel structures that route bit lines laterally and vertical-pillar structures that penetrate through layers vertically. In every structure, material selection and etch selectivity are critically important, but at the same time, ensuring adequate capacitance and managing thermal dissipation design are what ultimately determine commercial success. This is why close collaboration with device manufacturers — not just standalone technology development by equipment vendors — remains essential.
Lessons from the Huawei Overestimation Controversy
The structure of this NAURA-related coverage closely resembles the surge and subsequent cooling of the "vertical integration as an EUV workaround" enthusiasm that swept through Chinese tech circles just a few months earlier.
On May 25, 2026, at the IEEE ISCAS conference held in Shanghai, He Tingbo, head of Huawei's semiconductor division, unveiled new chip design technologies called the "Tau Scaling Law" and "LogicFolding." She claimed that by vertically folding and stacking logic circuits, it would be possible to achieve transistor density and performance equivalent to the 1.4nm node by 2031 — without using EUV lithography equipment at all. The announcement generated significant buzz.
Wccftech has positioned NAURA's etching achievement as a kind of "memory equivalent" of Huawei's LogicFolding. However, Huawei's announcement, too, drew strong skepticism and calls for caution from within the industry immediately following its unveiling.
Speaking to influential Chinese business outlet Caixin, Wu Zihao of Rong He Semiconductor Consulting pointed out that the transistor density Huawei claimed was calculated using coefficients that differ from industry-standard formulas, resulting in an overestimation of 35.7%. Applying the standard calculation formula strictly, the 3D transistor density Huawei touted for its Kirin chip — claimed at 238 million transistors per square millimeter — would shrink to 175 million.
Zhang Binlei of the Zhejiang University International Campus (ZICC) also told Caixin, while acknowledging LogicFolding as a genuine engineering endeavor, that it "must not be equated with a true physical 1.4nm node." Semiconductor research firm ICwise analyzed that folding and stacking circuits across multiple active layers causes a sharp rise in thermal density, making it extremely difficult to achieve commercially viable yields with a three- or four-layer stacked structure.
At the time, NVIDIA CEO Jensen Huang, while paying respect to LogicFolding as "a breakthrough for Huawei," dismissed the notion that it threatened TSMC's manufacturing leadership — noting that TSMC and Taiwan's broader semiconductor ecosystem have already been working on similar 3D packaging technologies for nearly a decade.
What the Huawei case demonstrated is a sobering fact: a massive gap exists between the "theoretical values of vertical stacking" trumpeted at conferences and keynote presentations, and the "commercial practicality" that requires clearing thermal issues, yield, and manufacturing cost hurdles. The excessive expectations placed on NAURA's etching technology risk falling into exactly the same trap.
When technical claims become intertwined with geopolitical rivalry narratives, exaggerated storytelling tends to take hold easily. Particularly in the semiconductor field, there is a tendency for theoretical possibilities or preliminary lab data to be reported as if they were an immediate miracle cure that neutralizes national sanctions networks. But in the world of manufacturing technology, progress cannot advance a single step unless both physical laws and economic viability are satisfied simultaneously. What is needed is calm, evidence-based scrutiny.
Key Indicators to Watch for Verifying Commercial Viability
The results NAURA presented at CSTIC 2026 — "selectivity exceeding 500x at 64 layer pairs, with silicon loss under 10Å during a 200nm lateral SiGe etch" — represent, when viewed strictly as lab data from a single equipment maker, a genuinely valuable advance in materials engineering. It does substantiate the company's technical determination to push its fine-processing etching capability to the absolute limit in an environment where access to EUV lithography equipment remains closed off.
However, this does not directly lead to the conclusion that "CXMT will overcome EUV constraints and mass-produce 3D DRAM." To accurately gauge the true value of this technology, it is necessary to step back from emotionally charged narratives and monitor the objective progression of facts.
Three things bear watching going forward. First, whether NAURA will formally disclose, as an official product specification, the specific model number of manufacturing equipment that realizes this process, along with wafer processing throughput (how many wafers per hour). Second, whether actual memory manufacturers, including CXMT, will officially acknowledge joint development or line adoption using this technology. And third, whether independent third-party research institutions or competing foundries succeed in reproducing comparable selectivity and uniformity results.
Between cleanly etching away an ultra-thin film on a lab test chip and running tens of thousands of wafers through a production line to recover a batch of functioning chips with a yield above 90%, numerous physical and economic hurdles still remain. Rather than overvaluing a single conference abstract, what is essential is a calm perspective that clearly identifies the limits of the disclosed data and the challenges that remain unresolved.
Which manufacturer will be first to achieve practical implementation on a commercial line, and whose equipment will be used to get there — the answers to these questions will require several more years and an enormous accumulation of verification experiments. NAURA's lab data is merely one signal marking the starting gun of that long marathon.