On August 26, 2026, NVIDIA announced a custom high-bandwidth memory design called "NVHBM." Unlike conventional configurations that place the memory controller on the XPU side, NVHBM moves it to the base die of the HBM stack. NVIDIA claims this increases bandwidth by up to 30% compared to standard HBM4E while cutting HBM power consumption by up to 15%. Because the freed-up space on the XPU can be repurposed for compute circuitry, NVIDIA also states that XPU compute die area can expand by up to 25%. The first collaboration partner is Amazon's semiconductor division, Annapurna Labs.
The significance of this announcement extends beyond simply speeding up memory. In addition to its own GPUs and NVLink, NVIDIA is moving to bring even the memory control scheme for other companies' XPUs under the umbrella of NVLink Fusion. However, the published figures are not benchmark results from actual hardware. Even within NVIDIA's own official materials, the area benefit is stated as up to 25% in one place and up to 30% in another. How well NVHBM performs as an actual product, and how far NVIDIA extends its design authority, are two separate questions that need to be assessed independently.
Moving HBM's Control Circuitry from the XPU to the Base Die
HBM stacks multiple DRAM dies and places them close to an AI accelerator. In the standard HBM4E configuration that NVIDIA uses as its baseline, the memory controller and the wide physical interface (PHY) consume area on the XPU die, and the wiring within the 2.5D package also becomes more complex. Area on an XPU built with a leading-edge process is expensive, and as more HBM is added, the competition for space with compute circuitry intensifies.
NVHBM integrates an NVIDIA-designed controller and a proprietary PHY into the bottommost base die of the HBM stack. The design replaces the connection between the XPU and HBM with a narrower, higher-performance link than before. The space freed up on the XPU side can then be used for matrix engines, caches, and other components, while wiring on the interposer also gains more room.
| Comparison Item | Standard HBM4E | NVHBM Claimed Effect |
|---|---|---|
| Memory Control | Controller placed on XPU side | NVIDIA-designed controller integrated into HBM base die |
| Bandwidth per Stack | Baseline; absolute value unspecified | Up to 30% increase |
| Power | Baseline | Up to 15% reduction (HBM portion) |
| XPU Compute Die Area | Occupied by wide PHY and support circuitry | Up to 25% increase |
What decreases under this configuration is power consumption within the HBM portion—it does not mean the entire XPU becomes 15% more power-efficient. Similarly, even if the freed-up area is used to add more compute circuitry, it does not follow that all workloads will speed up by the same proportion. Workloads bottlenecked by bandwidth, such as certain inference and training tasks, stand to benefit more, while workloads constrained by compute units or inter-XPU communication will see smaller gains.
30%, 15%, and 25% Are Not Measured on the Same Yardstick
NVIDIA's technical blog states that per-stack bandwidth increases by up to 30% compared to standard HBM4E. However, it does not disclose NVHBM's signal speed or interface width. Capacity and stack count also remain unknown. Nor is the specific HBM4E used for comparison identified. Samsung's HBM4E samples, which began shipping in May 2026, are rated at up to 3.6TB/s, but multiplying this by 1.3 to get 4.68TB/s cannot be treated as NVHBM's actual specification.
The area figures require even more caution. A table in both NVIDIA's corporate blog and technical blog states that XPU compute die area can increase by up to 25%. Meanwhile, the body text of that same technical blog states that "usable main die silicon increases by up to 30%." Since NVIDIA has not explained the difference in conditions between the two figures, it is reasonable at this point to read 25% as the conservative upper bound.
Two other figures appearing in the same materials—67% and 80%—refer to different things entirely. The 67% figure represents the area reduction in PHY and support circuitry, while the 80% figure represents the increase in usable silicon across an overall layout with simplified wiring. Neither should be added together with the 25% or 30% compute die area figures.
NVIDIA claims that combining these three improvements yields an overall 30% increase in end-to-end performance per XPU. However, the company has not disclosed the workload, number of HBM stacks, the XPU used for comparison, or the measurement methodology. At this stage, this 30% figure is a published estimate summarizing design-level benefits rather than a performance result that third parties can reproduce.
Prior Approaches to Custom HBM and How NVHBM Differs
The idea of moving functionality to the memory-side base die and connecting to the XPU via a narrower, faster link did not originate with NVHBM. In December 2024, Marvell announced a custom HBM configuration that connects the XPU and the HBM base die using high-speed serialized I/O. The company claims this saves up to 25% in area compared to standard HBM interfaces, cuts interface power by up to 70%, and increases the number of HBM stacks that can be mounted by up to 33%.
| Approach | Connection and Base Die | Primary Goal | Scope of Standardization |
|---|---|---|---|
| Marvell Custom HBM | High-speed serialized I/O; support logic moved to base die | Area, interface power, number of mountable stacks | Collaboration with Micron, Samsung, and SK hynix |
| JEDEC SPHBM4 | Reduces 2,048 pins to 512 via 4-to-1 serialization | Achieving HBM4-equivalent total bandwidth on organic substrates | Standardized industry-wide as JESD330-4 |
| NVIDIA NVHBM | NVIDIA-designed controller and PHY integrated into base die | Bandwidth, HBM power, XPU compute area | To be validated and supplied by multiple partners for NVLink Fusion |
Comparing these three approaches purely by the size of the numbers would be a mistake. Marvell's up to 70% reduction is measured against interface power, while NVIDIA's up to 15% reduction is measured against HBM power—these are not the same metric. SPHBM4 also narrows the connection, but its purpose is to establish a JEDEC standard that allows a shift from silicon interposers to organic substrates.
What distinguishes NVHBM is that NVIDIA's controller will be validated by multiple memory vendors and delivered to XPU developers together with NVLink, MGX racks, and software as part of NVLink Fusion. This could reduce the burden of designing and certifying memory on a per-XPU basis. In exchange, XPU makers incorporate NVIDIA's proprietary memory boundary into their designs. What NVIDIA calls a "standard NVHBM implementation" refers to standardization within its own program—it has not been announced as a JEDEC standard.
Trainium4 Supports NVLink Fusion, But the NVHBM-Equipped Generation Remains Undisclosed
Annapurna Labs is the first company collaborating with NVIDIA on NVHBM. The two companies say they are jointly exploring NVHBM and NVLink scale-up configurations to improve performance and efficiency in future AWS infrastructure. A joint announcement from NVIDIA and AWS also indicated the possibility that NVHBM could give Trainium access to faster, more power-efficient memory.
The relationship between Trainium4 and NVHBM remains unconfirmed. What has been explicitly stated as being adopted starting with Trainium4 is NVLink Fusion—there has been no announcement that Trainium4 will incorporate NVHBM. The start of collaboration with Annapurna Labs implies neither completed design nor customer certification. The timing of mass production, availability through AWS services, and which Trainium generation will adopt the technology have not been disclosed.
NVIDIA also stated that it plans to use the same technology behind NVHBM in its own future GPUs. Here too, the GPU name and launch timing remain undisclosed. Consequently, there is currently no basis for linking this to the Feynman generation or the year 2028.
Multiple memory vendors are expected to validate and supply NVHBM, but their names have not been disclosed either. Micron, Samsung, and SK hynix—companies already collaborating with Marvell—cannot simply be assumed to be NVHBM suppliers as well. Evaluating multi-vendor supply requires confirming that vendors are certified for the same XPU and that supply sources can actually be switched between them.
How to Read the Estimate of 15,000 Extra Units per 1GW
NVIDIA estimated that in a 1GW data center using XPUs that each consume 2,000W, the power savings from NVHBM could free up capacity equivalent to as many as 15,000 additional units of compute. A simple calculation—15,000 units × 2,000W—comes out to 30MW, or 3% of 1GW.
While 30MW is not a trivial amount, NVIDIA has not disclosed what proportion of XPU power is consumed by HBM, the data center's power usage effectiveness (PUE), or the power allocated to networking and cooling. How much of the 1GW can actually be directed to XPUs depends on PUE and facility configuration. There are still not enough conditions specified to directly translate a 15% reduction in HBM power into the ability to add 15,000 units in an actual data center.
Evaluating NVHBM properly will require confirming absolute bandwidth and latency, along with capacity. Total XPU power consumption and performance under real workloads are also essential. Add to that the timing of mass production, the names of memory vendors, and certification by multiple suppliers within the same package, and it will become possible to judge whether NVHBM has progressed from a design proposal to a deliverable platform. If NVIDIA meets these conditions, NVLink Fusion would become a foundation that unifies everything from inter-XPU connectivity to local memory.