A car approaches an intersection. A pedestrian's sudden dash into the road must be detected on a millisecond timescale, while traffic light changes can be tracked on a scale of seconds. Trends in road surface degradation appear over weeks to months. Handling this information across such vastly different timescales with a single sensor and a single processing circuit—this is where the fundamental difficulty of current semiconductor devices lies.
In 2001, German researcher Herbert Jaeger proposed the Echo State Network (ESN). Input signals are fed into a recurrent neural network (a reservoir) whose internal connections are fixed at random values, and only the output layer's weights are trained. This approach became known as reservoir computing, and it attracted attention as a framework for dramatically reducing the computational cost of time-series data processing. In conventional recurrent neural networks, all internal connection weights must also be trained, which chronically caused problems such as vanishing gradients and unstable training. Reservoir computing avoided this problem by "fixing" the internals.
In the 2010s, research began on "physical reservoir computing," which implements this reservoir not in software but in physical devices. Various material systems have been proposed, including optical circuits, MEMS oscillators, magnetic materials, and oxide semiconductors. Using physical devices allows the temporal changes in a signal to be naturally processed as the device's own dynamic response, potentially reducing power consumption by orders of magnitude compared to software simulation.
However, physical reservoirs shared a common structural problem: the device's time-response characteristics—how quickly it reacts to input and how quickly it returns to its original state—become fixed at the manufacturing stage.
Fixed "Time Constants" Rob Information
The performance of a physical reservoir is determined by how well the device's relaxation time constant matches the timescale of the input signal. If a rapidly changing signal is processed by a device with a slow response, it cannot keep up; if a slowly changing signal is processed by a device with a fast response, the information disappears.
Consider a concrete example. In heart rate monitoring, the heartbeat itself has a period of roughly one second, but signs of arrhythmia appear on a scale of minutes, and long-term decline in cardiac function must be captured as a trend over days to weeks. If a sensor's response speed is optimized for the one-second cycle, changes on the scale of minutes get averaged out and disappear, and trends over weeks cannot be detected at all. Conversely, if the sensor is tuned to weeks-long trends, it will miss abnormalities in individual heartbeats.
There have traditionally been two ways to address this problem. One is to perform preprocessing on the software side, converting the signal's timescale to match the device's response. The other is to prepare multiple types of devices with different response speeds and arrange them in parallel. The former increases computational cost and power consumption, while the latter complicates the manufacturing process. Both remained stopgap measures that accepted the premise that "the device's response is fixed."
In 2024, Nature Communications published a report on "wide reservoir computing" using a 3D-stacked crossbar array of tungsten oxide memristors. This was an attempt to process diverse timescales by arranging multiple reservoir layers in parallel, but it required using different materials and structures for each layer, leaving the complexity of the stacking process as a barrier to mass production.
The fundamental question is simple: is it impossible to change a single device's response speed after fabrication?
A Dual-Layer Gate Structure Achieves "Memory of Speed"
A research team led by Professor Choi Shinhyun (Chair Professor) of the KAIST School of Electrical Engineering and the School of Semiconductor Technology answered this question by stacking two functional layers within a transistor's gate stack.
The device they developed was named the Programmable Dynamic Memtransistor (PDM). The key points of its structure are as follows.
Within the gate insulating film, two layers are embedded: a charge storage layer and a charge trap layer. The charge storage layer receives the input signal, temporarily storing charge before releasing it. This layer is responsible for the device's "dynamic response"—that is, the decay of current over time. Meanwhile, the charge trap layer non-volatilely modulates the semiconductor's band structure by trapping (capturing) electrons. The amount of trapped electrons determines the speed at which charge escapes from the charge storage layer—in other words, the relaxation time constant.
Here lies the decisive feature: the state of the charge trap layer is retained even when the power is turned off. Once the response speed is set, no continuous external bias supply or input data preprocessing is needed afterward. The device "remembers" at what speed it should respond, and continues to operate at the same speed after the next power-up. This applies the same physical principle by which flash memory retains data via charge quantity, but here it is applied to controlling response speed instead.
The tuning range confirmed experimentally spans approximately fivefold in relaxation time constant and more than tenfold in characteristic frequency. A single device type can be set to multiple states, from "fast response" to "slow response," purely by programming. There is no need to change the manufacturing line. Simply by electrical writing, different response speeds can be assigned to different elements on the same chip.
Configuring a "Wide Reservoir" from a Single Device Type
The true value of PDM is realized not in a single device but in an array configuration. The research team arranged multiple PDMs, each set to a different response speed, in parallel, constructing a "wide reservoir computing" system in which each element extracts information from a different timescale simultaneously.
Why does this configuration work? The computational power of reservoir computing is determined by how effectively the reservoir can transform the input signal into a high-dimensional feature space. When elements with different time constants are arranged in parallel, each element "sees" the signal through a different time window, resulting in a richer high-dimensional representation overall. The research team showed that this parallel arrangement of diverse time responses increases the rank (the number of linearly independent components) of the reservoir state matrix, thereby improving prediction accuracy.
The benchmark task results are summarized in the table below. The paper reports the relative ratio of normalized mean squared error (NMSE), using the single-reservoir configuration as the baseline. Since absolute values vary depending on the signal's amplitude and frequency composition, the paper adopts a comparison based on ratios.
| Task | Single Reservoir (Fixed Response) | PDM Array (Wide Reservoir) | Improvement Ratio |
|---|---|---|---|
| Superimposed multi-frequency oscillator prediction | NMSE = 1.0 (baseline) | NMSE ≒ 0.025 | About 40x |
| Multivariate chaotic signal (Lorenz attractor) prediction | NMSE = 1.0 (baseline) | NMSE ≒ 0.25 or less | 4x or more |
| Power consumption | Conventional software-based system | Achieves comparable accuracy at lower power consumption | No quantitative comparison in the paper |
Note: NMSE values are relative, normalized to the single-reservoir configuration's error as 1.0. Absolute error depends on the parameters of the input signal. Regarding power consumption, the paper states a "significant reduction," but no specific figures are provided.
For Lorenz attractor prediction, the paper reports achieving accuracy comparable to software-based reservoir computing while significantly reducing power consumption.
Structural Differences from Competing Approaches
PDM is not the first attempt to control the time response of a physical reservoir. The table below summarizes a comparison with major approaches.
| Item | Conventional Physical Reservoir | 3D-Stacked Memristor (2024) | ADRN Proposal (Simulation) | PDM (This Study) |
|---|---|---|---|---|
| Control of response speed | Fixed at fabrication | Different elements used per layer | Real-time control via ReRAM resistance | Non-volatile programming via charge trap layer |
| Persistence of control | Not needed (fixed) | Not needed (fixed) | Continuous bias required | Non-volatile (retained without power) |
| Level of demonstration | Experimentally demonstrated | Experimentally demonstrated | Circuit simulation only | Experimentally demonstrated |
| Manufacturing compatibility | Depends on material system | Complex stacking process | CMOS-compatible (by design) | Fully compatible with commercial semiconductor process materials |
| Support for diverse timescales | Single scale only | Multiple scales (achieved via structure) | Multiple scales (achieved via resistance value) | Multiple scales (achieved via programming) |
The advantage of PDM lies in its ability to achieve diverse response speeds using a single device structure and a single manufacturing process. Unlike the 3D-stacked approach, there is no need to stack different elements, and unlike the ADRN proposal, no continuous power supply is required. Response characteristics can be changed purely through electrical programming, without adding manufacturing steps—an advantage directly tied to cost and yield in mass production.
Path to Mass Production and Remaining Questions
The research team claims that PDM is fully compatible with materials widely used in commercial semiconductor manufacturing processes. The fact that co-authors Young Taek Oh and Jae-Duk Lee of Samsung Electronics' Semiconductor R&D Center are listed among the authors also hints at a connection with industry.
However, many points remain to be verified before practical application. First, this achievement is a demonstration on a laboratory-scale array, and device-to-device variation and yield at large-scale integration remain unverified. The tuning range of the relaxation time constant is reported as approximately fivefold, but whether this range is sufficient to fully cover the breadth of timescales demanded by real-world sensor data (from microseconds to minutes) depends on the application scenario.
Furthermore, while the benchmark tasks presented in the paper (superimposed oscillator prediction, Lorenz attractor prediction) are standard evaluation tasks used in the reservoir computing field, performance in actual application scenarios such as autonomous driving and robotics requires separate verification. Professor Choi stated, "We hope this will become a foundational technology that improves the performance of AI devices such as autonomous vehicles, robots, and wearables while reducing power consumption," but this is a future outlook, not currently demonstrated performance.
Another challenge is the long-term reliability of the charge trap layer. Points such as how much endurance the non-volatile trap state has against repeated rewriting, and whether trapped charge leaks in high-temperature environments, are verification items that cannot be avoided for automotive and industrial applications. In the flash memory field, decades' worth of reliability data have accumulated for this type of challenge, but equivalent data for PDM's response-speed-control application does not yet exist.
The paper was submitted on October 29, 2025, accepted on June 23, 2026, and published in Nature Communications on July 4 of the same year. It has undergone peer review, and verification of reproducibility is left to future independent replication studies.