Samsung Electronics and SK hynix are reportedly set to collaborate on Qualcomm's "High Bandwidth Compute (HBC)" memory technology for AI inference. South Korean semiconductor trade outlet The Elec reported the news, citing remarks made by Qualcomm EVP Durga Malladi on August 26, 2026. According to the report, both companies will develop HBC while continuing their core HBM business, with TSMC supporting technology integration and advanced packaging. The race to speed up memory is beginning to split into two branches: moving data to the processor faster, versus finishing computation near the memory itself.
Two Korean Firms Developing HBC Alongside HBM
According to The Elec, Malladi visited South Korea after Qualcomm's Investor Day and met with the two major memory makers. Since Qualcomm had criticized HBM's power consumption and data-movement costs at its Investor Day, Malladi reportedly expected pushback. Instead, both companies actively proposed cooperating on HBC, and are said to now be participating in its development alongside their respective HBM roadmaps.
The reported division of labor is clear. Qualcomm will design the compute die placed beneath the DRAM stack along with the TSVs, and integrate the overall system. Samsung and SK hynix are expected to handle stacking the DRAM chips, while TSMC supports integration and packaging across the various technologies. The report also states that first-generation HBC has already entered Qualcomm's labs for verification.
However, the four companies have not jointly announced any contract or production allocation for HBC. There is no official announcement yet confirming order volumes or specific process responsibilities for Samsung Electronics, SK hynix, or TSMC regarding HBC specifically. Nor has it been determined that the two Korean firms will become exclusive suppliers.
HBC Chooses to Move Computation Rather Than Widen Interconnects
In generative AI inference, workload characteristics differ between prefill—which processes input in bulk—and decode, which generates responses one token at a time. According to Qualcomm's explanation, decode repeatedly reads model weights and long context from memory, meaning data supply, rather than compute speed, tends to limit processing throughput. HBM has expanded its connection to the processor, but the data it handles still travels out of memory and over to the XPU.
HBC changes this division of labor. It stacks LPDDR-family DRAM vertically, connected via TSVs to a compute die below. Processes that read large volumes of data are executed near the memory, passing only the reduced results to the external main accelerator. The main accelerator continues handling complex, flexible processing, while the HBC side takes on data-movement-dominant tasks. In other words, HBC is less a substitute for CPUs or AI accelerators and more a dedicated compute-and-memory layer that offloads part of the inference workload.
Custom HBM has also begun incorporating sophisticated logic base dies. The difference between the two approaches lies not in whether logic exists, but in how much computation that logic is allowed to perform. Custom HBM optimizes the interface and control passed to the external XPU for each customer. Qualcomm describes HBC as a design that completes memory-bandwidth-intensive computation within or directly beneath the stack itself.
Why 133TB/s and HBM4's 3.3TB/s Aren't Comparable
The 133TB/s figure Qualcomm cites for AI250 refers to "effective memory bandwidth" usable for computation on a single card. The target is 18 times that of the AI200's LPDDR5X configuration, and 54 times the AI200 for the AI300, which uses HBC Gen 2.
Meanwhile, the maximum 3.3TB/s figure for HBM4, which Samsung has begun mass-producing, represents the physical memory bandwidth at which a single stack outputs data externally. Even though 133TB/s and 3.3TB/s share the same "bytes per second" unit, they differ across multiple dimensions: card versus stack, internal versus external, and effective versus interface value. The speed difference between HBC and HBM4 cannot be derived from these two published figures.
The "6x HBM" claim also comes with caveats. What Qualcomm presents is its own estimate of bandwidth per watt, normalized to card-level units based on competing products' published specifications. The "200x SRAM" figure compares capacity per watt at the rack level. The 18x figure compares against the previous-generation AI200, the 6x figure compares power efficiency against the HBM approach, and the 200x figure compares capacity efficiency against the SRAM approach—three separate metrics. At this stage, all of these remain design targets rather than benchmarks reproduced on actual hardware by third parties.
These definitional nuances don't negate HBC's potential value. If internal memory bandwidth can be used directly for computation, it may be possible to process more data with less movement than a design that simply widens external I/O. But actual token generation speed will depend on what proportion of computation can be offloaded to HBC and how well the software is implemented. Results will also vary with computational precision and batch size. Qualcomm has not yet disclosed the detailed workload used to calculate the 133TB/s figure.
Why Samsung and SK hynix Are Hedging Their Bets
For Samsung and SK hynix, participating in HBC isn't an either-or choice against their HBM business. Samsung announced mass production and commercial shipment of HBM4 in February 2026, citing up to 3.3TB/s per stack and capacities of 24GB to 36GB. SK hynix, too, is centered on HBM4 while expanding its development scope into customer-specific custom HBM and memory-logic integration.
At the same time, both companies' R&D is converging toward the boundary between memory and logic. Samsung's HBM4 uses a 4nm logic base die, and the company cites joint optimization between its memory and foundry divisions along with in-house advanced packaging capability as the foundation for mass production. SK hynix has adopted TSMC's advanced logic process for the HBM4 base die, and explicitly names "3D Stacked DRAM on Logic" as a future candidate technology. The DRAM stacking and memory-logic coordination required for HBC overlap with capabilities both companies are already honing for other product lines.
Even as HBM remains the mainstream choice for AI training and inference, inference-dedicated systems won't necessarily always converge on the same solution. For decode workloads that read models repeatedly, reducing power by relocating where processing happens can sometimes be more effective than simply increasing external bandwidth. By protecting their HBM market position while also positioning themselves to capture supply opportunities if compute-embedded memory expands, Samsung and SK hynix's parallel investment in HBC is a strategy that keeps both paths open.
TSMC's 3D Integration and What Remains Before 2027
Even if HBC reduces data movement, manufacturing challenges remain. DRAM and logic differ in both process technology and thermal behavior, and if even one die in a stack turns out defective after stacking, the loss to the entire package can be significant. Manufacturers must form numerous short TSV connections, supply power while dissipating heat, and secure yields adequate for mass production.
TSMC's SoIC can 3D-stack dies of different functions and process nodes with sub-10µm connection pitch. Its 3nm stacking technology entered mass production in 2025, and the framework for incorporating stacked chips into CoWoS or InFO packaging is already established. However, The Elec's report of TSMC's involvement in HBC does not necessarily mean SoIC will be adopted. Neither the packaging method name nor the process node for the compute die has been disclosed.
Qualcomm cites reduced dependence on the expensive, supply-constrained packaging required for HBM as an advantage of HBC. This is not the same as saying advanced packaging becomes unnecessary. Even if the interconnect carrying all data between HBM and the external XPU changes, the process of vertically integrating DRAM with logic will still be required. The report of TSMC's involvement suggests not that the packaging burden disappears, but that the emphasis may shift from horizontal connections to vertical integration.
Caution is also warranted regarding product timing. While The Elec reported commercialization and shipment of first-generation HBC in 2027, Qualcomm's official language states that "commercial samples of AI250 and HBC Gen 1 are planned for mid-2027." Sample availability marks the beginning of customer evaluation, not mass production shipment. Commercial samples for AI300 and HBC Gen 2 are slated for 2028.
What should be verified by mid-2027 is not the 133TB/s figure itself, but the actual tokens-processed-per-watt and operational stability achieved with real LLMs. Once Samsung, SK hynix, and TSMC officially confirm their roles, customers complete their evaluations, and 3D stacking yields reach mass-production levels, HBC will transform from a challenge to HBM into an AI inference platform that customers can actually choose.