This physical constraint is known in the semiconductor industry as "Boltzmann tyranny." At room temperature, the amount of gate voltage change required to switch a conventional transistor's current by one order of magnitude (10x)—known as the subthreshold swing (SS)—is theoretically limited by thermodynamic law to a lower bound of approximately 60 mV/decade. As long as this limit exists, supply voltage cannot be significantly reduced, and increasing integration density inevitably runs into a "power wall" of rising heat density and power consumption.
Tunnel field-effect transistors (TFETs), which exploit quantum mechanical tunneling, have long been positioned—including in guidelines such as the International Roadmap for Devices and Systems (IRDS)—as the leading candidate for breaking through this Boltzmann limit. An international research team led by the Hong Kong Polytechnic University (PolyU) has now developed a two-dimensional heterostructure TFET that, by skillfully combining atomically thin materials, simultaneously achieves steep switching characteristics well below the Boltzmann limit at room temperature and an on-current robust enough for practical logic circuit operation. The findings were published in the journal Science on August 27, 2026 (DOI: 10.1126/science.adx6059).
The Thermionic Emission Wall and the Power Dilemma of the Boltzmann Limit
Conventional field-effect transistors (MOSFETs) control current by raising and lowering an energy barrier between the source and drain using an electrostatic potential applied to the gate electrode. When the switch is off, a high barrier blocks electrons from passing through; when voltage is applied to the gate to lower the barrier, electrons flow into the drain side.
Under this operating principle, the charge carriers that flow over the barrier follow a thermal energy distribution governed by Maxwell-Boltzmann statistics. At temperature $T$, the probability of an electron occupying an energy level $E$ is governed by the proportional term (where is the Boltzmann constant). When the barrier height is varied by the gate voltage, the number of electrons thermally excited over the barrier changes exponentially. The theoretical limit of the subthreshold swing (SS) derived from this relationship is expressed as follows:
Here, $q$ is the elementary charge, is the depletion layer capacitance, and is the gate oxide capacitance. Even assuming ideal electrostatic control (), the mathematical lower bound of SS at room temperature () is approximately 59.6 mV/decade (commonly referred to as 60 mV/decade). In other words, to clearly switch from "off" to "on" by changing the current by 6 orders of magnitude (a factor of one million), a minimum voltage range of is required. In actual integrated circuits, an even higher supply voltage of around 800 mV must be continuously provided to secure margins against manufacturing variation and to suppress off-state leakage current.
The dynamic power consumption of a transistor follows the relationship with respect to operating frequency $f$, load capacitance $C$, and supply voltage . Because power is determined by the square of the voltage, the inability to lower the supply voltage is a decisive constraint on power efficiency for the entire circuit. Even today, as gate lengths in advanced semiconductor processes have been scaled down to nanometer dimensions, the primary reason operating voltages remain stuck just below 1 V is this physics of thermionic emission.
The TFET, which exploits band-to-band tunneling (BTBT), was devised to overcome this wall. Rather than making electrons "jump over" the barrier, a TFET controls the energy band structure of the source and channel to make electrons "tunnel through" the barrier to conduct current. Because the broad, thermally spread energy distribution can be physically cut off (energy filtering) at the edge of the energy bandgap (the band edge), steep switching below the thermionic emission limit of 60 mV/decade becomes possible.
Steep Switching Achieved by Combining 2D Bismuth with Indium Selenide
A collaborative research team led by Assistant Professor Zehan Wu, Professor Jiannong Wang, and Professor Jianhua Hao of the Hong Kong Polytechnic University—with participation from the National University of Singapore, the Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design—designed a new TFET device using a heterojunction of two-dimensional (2D) materials.
What the team constructed was an ultrathin heterostructure of bismuth () and indium selenide (), precisely controlled down to the atomic layer level. This device was deposited on a standard centimeter-scale silicon substrate using pulsed laser deposition (PLD).
As a result of experiments, this Bi/InSe heterojunction TFET successfully maintained a steep SS value well below the Boltzmann limit of 60 mV/decade across an entire six-order-of-magnitude current change range at room temperature (300 K). Importantly, the steep characteristics were maintained not just momentarily in a localized voltage region, but across the entire practical switching range from off-state to on-state.
Furthermore, the gate voltage range required to switch the device was only about 160 mV. Compared with a state-of-the-art Si MOSFET, which requires a gate voltage range of about 800 mV to secure an equivalent on/off current ratio, this represents a compression of the required control voltage swing (160 mV) to roughly one-fifth (20%).
Moreover, the device in this study achieved an extremely high on/off current ratio (over six orders of magnitude) while recording an output current (on-current) reaching several at maximum. In contrast to many previous laboratory-level steep-SS devices, which could only pass minuscule currents in the nanoampere (nA) range or below—raising doubts about their applicability to practical circuits—this study experimentally demonstrated a current value approaching the practical range needed for circuit operation.
The Physical Mechanism: Band Alignment Driven by a Semimetal-to-Semiconductor Phase Transition
Although the concept of the TFET itself has been proposed since the 1970s, the path to practical implementation has been fraught with difficulty. The biggest obstacle has been the fact that achieving both a steep SS and a large on-current is, in principle, extremely difficult to reconcile.
To obtain a steep SS, the tunneling barrier must be made thick to block thermally excited leakage current in the off-state and to enable sharp energy filtering. However, making the barrier thicker exponentially reduces the tunneling probability of electrons (transmission coefficient) in the on-state, significantly lowering the output current. Conversely, making the tunneling barrier thinner or using materials with an extremely narrow bandgap increases the on-current, but also increases off-state leakage current and trap-assisted tunneling (TAT) through defect states, degrading SS to above 60 mV/decade.
To break this trade-off, the research team focused on dimensional control of bismuth. In its bulk (bulk-state) form, metallic bismuth behaves as a "semimetal," with the top of the valence band and the bottom of the conduction band slightly overlapping. However, when its layer thickness is reduced via PLD to the level of a few atomic layers (nanoscale), quantum confinement effects split the electron energy levels and open up an energy gap. A phase transition from semimetal to "semiconductor" occurs.
By joining this 2D-semiconductorized ultrathin bismuth layer with indium selenide (InSe), a layered semiconductor with high electron mobility, an ideal band alignment was formed.
When voltage is applied to the gate electrode, the energy bands of the 2D bismuth layer and the InSe layer rapidly overlap, and the width of the tunneling barrier becomes extremely thin. By combining the advantage of a 2D material's small electron effective mass with the sharp density of states from a steep band edge, the team succeeded in blocking thermal leakage current while maintaining a high tunneling transmission probability.
The adoption of PLD (pulsed laser deposition) for the film deposition process also played a key role. PLD is a technique in which a high-energy laser pulse is directed at a target material to generate a plume, depositing atomic layers onto a substrate. Compared with chemical vapor deposition (CVD) or mechanical exfoliation, it can form sharp and clean interfaces between different 2D materials without compromising crystallinity. Eliminating unwanted leakage current pathways caused by defects is the physical factor behind the device's ability to maintain low SS across a wide six-order-of-magnitude current range.
Comparison with Prior TFET Research and Performance
To properly evaluate TFET performance, it is necessary to distinguish between theoretical predictions from simulations (TCAD calculations) and experimental values measured from actually fabricated physical devices. Even structures that show remarkable characteristics in theory often see their experimental values significantly degraded in the presence of real interface defects and scattering caused by lattice mismatch—a common phenomenon in this field.
The table below compares the characteristics of the Bi/InSe TFET from this study with representative conventional field-effect transistors and past steep-SS devices.
| Device structure / architecture | Demonstration form | Subthreshold swing (mV/dec) | On-current () | On/off current ratio | Operating voltage range (mV) | Substrate / process scale | Source / reported year |
|---|---|---|---|---|---|---|---|
| Standard Si MOSFET (theoretical limit) | Theoretical | 59.6 (room-temperature lower bound) | 300 mm wafer | Boltzmann thermodynamic limit | |||
| Ge / heterojunction TFET | Experimental | Minimum 3.9 / average 31.1 | Micro-exfoliated flake substrate | Wu et al. (2025) | |||
| Typical 2D transition metal dichalcogenide TFET | Experimental | (localized region only) | $10^3 - 10^5$ | $\sim 1000$ | Laboratory-scale substrate | Prior research | |
| Ideal carbon nanotube / 2D TFET | Numerical simulation | Simulation (TCAD) | Various theoretical predictions | ||||
| Bi / InSe ultrathin heterojunction TFET | Experimental | Sustained across 6 orders of magnitude | Level of several | (over 6 orders) | ~160 | Standard cm-scale Si substrate | Wu et al., Science (2026) |
Many previously reported experimental TFETs, even when they recorded an SS below 60 mV/decade, achieved this only within a narrow gate voltage range corresponding to a change of just one or two orders of magnitude in current. Furthermore, on-currents were typically limited to a few nanoamperes, lacking the fan-out capability needed to charge and discharge downstream logic gates at sufficient speed.
As organized in a 2025 review in the journal Interdisciplinary Materials (DOI: 10.1002/idm2.70011) and elsewhere, while some heterojunction devices such as Ge/ have achieved both low SS and room-temperature on-currents on the order of , they have struggled with uniform film deposition and compatibility with Si substrates. The distinguishing feature of this Bi/InSe device is that it was grown directly on a centimeter-scale Si substrate via PLD, and experimentally demonstrated on-currents of several while maintaining low SS across a wide six-order-of-magnitude drain current range.
Manufacturing Process and the Reality of the Integration Roadmap
The research team argues that 2D material deposition using PLD could become a practical option for high-precision, wafer-scale manufacturing of next-generation transistors with extremely short channels. They also point to the process's compatibility with existing silicon CMOS manufacturing—since it can be performed on standard silicon substrates—and its potential applicability to future high-efficiency chips for AI hardware, as future prospects.
However, these claims do not mean that "practical integrated circuits can be manufactured immediately." There remains a vast engineering gap between fabricating a single device at the research stage and lining up billions of devices without defects on a semiconductor manufacturing line.
First, what has been demonstrated here is a single-device evaluation on a centimeter-scale substrate fragment; film thickness uniformity and defect density control across the full surface of a 300 mm (12-inch) wafer—the current standard in semiconductor front-end processing—have not been verified. While pulsed laser deposition is well-suited to fundamental research on high-quality oxide and chalcogenide thin films, it has a limited track record of mass production compared with atomic layer deposition (ALD) or industrial MOCVD (metal-organic chemical vapor deposition) in terms of uniform deposition over large-area wafers and mass-production throughput.
Second, the roadmap mentioned in press releases and elsewhere—regarding "applications to power-efficient chips for AI"—represents a statement of future expectations based on the fundamental physical properties demonstrated in this study. At this point, no circuit-level demonstration data has been shown using this Bi/InSe TFET to construct an inverter, ring oscillator, or basic logic gate.
A single transistor exhibiting excellent static characteristics and that same transistor operating correctly in step with a clock frequency once integrated into a circuit are separate technical challenges. Toward practical circuits, further reduction of parasitic capacitance and contact resistance, as well as further reduction of trap states at the gate oxide interface, will be essential.
Unresolved Questions and Challenges Toward Practical Implementation
While this study presents groundbreaking figures as a single experimental result, numerous challenges remain to be verified before this can be established as a mature semiconductor technology.
Judging from the dataset registered in the Hong Kong Polytechnic University data repository (DOI: 10.60933/PRDR/A458PH), the publicly available experimental data is based on a limited sample size. In modern processors that integrate hundreds of millions to tens of billions of transistors, variation in threshold voltage () and SS values between individual devices must be kept extremely small. Statistical data on the yield achievable within a single wafer and the degree of device-to-device variation will need to await future replication studies and additional reports.
Furthermore, to construct CMOS (complementary MOS) logic circuits, n-type transistors (which use electrons as carriers) and p-type transistors (which use holes as carriers) must operate as a pair on the same substrate. No solution has yet been presented for how to fabricate, within the same process, a complementary p-type TFET with equal or better steepness and on-current to match the Bi/InSe-based TFET reported here.
Additionally, verification of device robustness under conditions assuming practical use—such as reliability under long-term electrical stress, the presence or absence of hysteresis, and characteristic changes under high-temperature operating environments—remains a task for the future.
The significance of this achievement for semiconductor physics is substantial in that it demonstrates that the physical limit of thermionic emission can be overcome via quantum tunneling, and that steep switching and a practical on-current can coexist in a single laboratory device. Whether this demonstration of physical principles will translate into industrial-scale integrated circuit technology depends on the future maturation of large-area film deposition techniques and demonstration of implementation at the circuit level.