As of 2026, NVIDIA's GPUs and AMD's AI accelerators have shifted to designs that place a dozen or more HBM (High Bandwidth Memory) stacks and logic dies side by side within a single package. The area of the interposer—the intermediate substrate connecting these chips—has been expanding year after year, and TSMC's CoWoS is now mass-producing 5.5-reticle interposers (roughly 4,700 mm²) in 2026.
What exactly is a "reticle"? Semiconductor lithography equipment reduces the circuit pattern on a mask to one-quarter scale before projecting it onto the wafer. The maximum area that can be exposed in a single pass is 26mm × 33mm, or about 858 mm²—this is called one reticle. When an interposer design exceeds this area, multiple exposures must be stitched together, a process that sharply increases the risk of alignment errors and yield loss.
The semiconductor industry has addressed this constraint through chiplets—combinations of smaller dies. But as AI workloads grow, the interposers that connect these chiplets have themselves ballooned in size, running into the reticle limit once again. At a technology symposium in April 2026, TSMC Vice President Zhang stated that the company would expand to 9.5 reticles in 2027 and 14 reticles in 2028, ultimately outlining a "System-on-Wafer (SoW)" concept that uses an entire wafer as the interposer.
The problem is that placing a large square interposer on a round wafer wastes material at the edges. A 300mm wafer yields only four 8-reticle interposers.
Rapidus's Answer: Square Glass
In August 2026, Rozalia Beica, Packaging CTO at Rapidus Design Solutions, presented the company's roadmap at the OCP APAC Summit. The plan calls for expanding interposer area in stages—from 4 reticles (3,320 mm²) to 6 reticles (4,980 mm²), and ultimately to 8 reticles (6,640 mm²) by 2030. An 8-reticle interposer corresponds to a square roughly 81mm on each side.
On raw numbers alone, this falls short of TSMC's 14-reticle plan. But Rapidus isn't competing on size. It's betting on a fundamentally different manufacturing approach.
Beica's comparison was straightforward: how many 8-reticle interposers can be obtained from each type of substrate?
| Substrate Format | Yield (8-Reticle Equivalent) | vs. 300mm Wafer |
|---|---|---|
| 300mm round wafer | 4 | 1× |
| 300×300mm panel | 9 | 2.25× |
| 510×515mm panel | 36 | 9× |
| 600×600mm panel | 49 | 12.25× |
Using a 600mm square panel makes it possible to manufacture interposers of the same area more than 12 times more efficiently than on a 300mm wafer. This is because the material waste that occurs at the edges of a round wafer disappears, in principle, with a square panel.
The material choice matters too. Rapidus selected glass rather than silicon as the interposer substrate. Glass offers superior surface flatness compared to silicon, and its coefficient of thermal expansion can be tuned for specific applications. This flatness directly affects dimensional precision when forming high-density redistribution layers (RDL)—the wiring layers that route a chip's terminals out to the package. Glass is also said to have better electrical properties than silicon, contributing to improved power efficiency in AI chips.
Repurposing the LCD Industry's Legacy for Semiconductors
A 600mm-square glass substrate is an unusual size by semiconductor industry standards. But it's an everyday material in the liquid crystal display industry. Rapidus deliberately drew on this cross-industry expertise, hiring engineers from Japanese display makers including Sharp to address processing challenges such as glass cracking and warping.
In June 2025, Rapidus began prototyping at Rapidus Chiplet Solutions (RCS), established within Seiko Epson's Chitose facility in Chitose, Hokkaido. At SEMICON Japan 2025 that December, the company unveiled what it called the world's first large glass interposer prototype. Interposers cut from the 600mm-square glass substrate reportedly offer 30 to 100% more surface area than conventional products.
On the equipment side, collaboration with Lam Research is central to the effort. Yasumitsu Orii, head of Rapidus's engineering center, said: "At the core of the 2.xD packaging technology that forms RDL on 600mm-square glass carriers is Lam's panel-level solution—specifically the copper electroplating tool 'Kallisto,' which supports 600mm panels." Kallisto is designed to switch panels from horizontal transport to a vertical orientation, securing them on chucks as they move between plating chambers; the tool can reach up to 18 meters in overall length. Lam Research is also developing a next-generation production tool called "Phoenix" at the same site.
RCS began full-scale operation in April 2026. Japan's Minister of Economy, Trade and Industry, Ryosei Akazawa, attended the opening ceremony, once again signaling the Japanese government's commitment to supporting the effort. Rapidus's equipment installation is ultimately planned to reach roughly 300 tools.
Comparing Rapidus and TSMC: Same Goal, Different Routes
Rapidus and TSMC are both tackling the same challenge—scaling up AI chip packaging—but their approaches differ structurally.
| Comparison | TSMC (CoWoS) | Rapidus (Panel-Level) |
|---|---|---|
| Interposer material | Silicon | Glass (RDL organic interposer) |
| Substrate shape | 300mm round wafer | 600×600mm square panel |
| 2026 interposer scale | 5.5 reticles (mass production) | 4 reticles (3,320 mm², prototype stage) |
| 2028 target | 14 reticles | Start of mass production (glass interposer) |
| 2030 target | SoW-X (whole-wafer, ~40-reticle equivalent) | 8 reticles (6,640 mm²) |
| Manufacturing premise | Extension of front-end wafer fab processes | Repurposed LCD panel manufacturing know-how |
TSMC is pushing its existing wafer-based process to its limits, ultimately moving toward SoW, in which an entire wafer serves as a single package—a technology already adopted by Cerebras Systems. Rapidus, by contrast, has chosen to eliminate the constraint of the wafer's round shape altogether, maximizing area efficiency through a panel-based approach.
Which approach will prove superior remains an open question. TSMC has a track record of mass production and an established customer base. Rapidus's 600mm panel method has yet to be proven for mass-production yield and reliability.
The "IIM" Model: Integrating Front-End and Back-End Processes
What Beica presented at the OCP APAC Summit wasn't limited to packaging technology. She also introduced a manufacturing model called "Innovative Integration and Manufacturing (IIM)," which uses AI and sensor data to monitor wafer conditions in real time, predict defects, and feed the results back into the design process—running design and manufacturing optimization simultaneously.
Beica described the facility as "the world's first fab to integrate front-end and back-end processes under one roof"—a vision in which IIM-1 (the front-end fab for 2nm logic) in Chitose and the adjacent RCS (the back-end packaging site) operate as a unified system through shared data and processes.
Rapidus's Advanced Packaging portfolio covers flip-chip BGA, 2.5D silicon interposers, panel-level RDL organic interposers, both bridge and bridgeless configurations, and 3D stacking via hybrid bonding. By 2030, the company envisions integrating sub-2nm logic, HBM, chiplets, optical interconnects, hybrid bonding, and panel-level packaging into a single system.
A ¥2.6 Trillion Bet and Unanswered Questions
The Japanese government plans to invest a total of ¥2.6 trillion (roughly $16.3 billion) in Rapidus by the end of March 2027. In April 2026, it approved an additional ¥631.5 billion (roughly $4 billion) in support. In February 2026, the company also secured ¥167.6 billion in investment from 32 private companies, including Canon, Fujitsu, NTT, SoftBank, and Sony Group.
Whether this massive investment translates into results, however, hinges on several unresolved conditions.
First is the quality of mass-produced 600mm-square glass. While Rapidus achieved a "world first" at the prototype stage, it has not yet been demonstrated whether warping and cracking can be controlled at scales of hundreds or thousands of panels. Lam Research itself positions Kallisto as a tool for "low-volume production and R&D," and Phoenix, the mass-production tool, is still under development.
Second is customer qualification. As Orii noted in an interview with Rapidus, mass production cannot begin until the technology clears two stages of qualification—technology qualification and product qualification. The back-end pilot line only began full-scale operation in April 2026, and no timeline has been given for completing qualification.
Third is the competitive dynamic with TSMC's SoW concept. If TSMC realizes its plan to integrate 64 HBM stacks with SoW-X by 2029, the competition over interposer area could shift to an entirely different dimension. Where Rapidus's 8-reticle panel approach will stand at that point depends on how AI chip design philosophy evolves.
Reportedly, Rapidus was the only company to propose an 8-reticle interposer in NEDO's public call for proposals. As one of the company's engineers recalled, "About a year later, 8 reticles became the industry's standard way of thinking, and discussion had even moved on to the need for 9.5 reticles." That forecast proved correct. The question now is whether it will hold up on the mass-production floor as well.