When will Rapidus's 2nm mass production ramp up, and how far behind TSMC and Samsung is it? That single question has dominated the attention of semiconductor industry watchers. But the collaboration announced by Rapidus and Cadence on July 17, 2026 brought a different competitive axis into view—one separate from the mass-production timeline. The focus has shifted to whose design tools companies will build on. Cadence has, in near-simultaneous fashion, joined forces with both Rapidus and Intel Foundry—two challengers chasing leading-edge nodes—to build design infrastructure centered on agentic AI.
A Redesigned Development Environment Unveiled at CadenceLIVE Japan
On July 17, 2026, Rapidus announced a collaboration with Cadence Design Systems (hereafter "Cadence") at CadenceLIVE Japan 2026. At the core of the partnership is the integration of Cadence's agentic AI platform, "InnoStack AI Super Agent," into Rapidus's proprietary design support tool, "Raads" (Rapidus AI-Agentic Design Solution). The two companies explained that this integrated environment will automate the entire design flow, from architecture exploration through implementation to sign-off. Alongside this, two new tools—"Raads Navigator" and "Raads Indicator"—were also introduced, tasked with supporting quality assurance and resolving design challenges.
The numerical target set out by this collaboration is to accelerate design turnaround time (TAT) by up to 2x compared to conventional flows. Atsuyoshi Koike, Representative Director, President and CEO of Rapidus, stated, "By evolving Raads and integrating it with Cadence's InnoStack AI Super Agent, we will strengthen our design environment through the use of AI agents." Anirudh Devgan, President and CEO of Cadence, commented, "By combining Cadence's InnoStack AI Super Agent with Rapidus's Raads, we will extend agentic AI across the leading-edge semiconductor ecosystem, enabling our customers to boost productivity, accelerate design convergence, and bring more advanced silicon to market faster."
Rapidus is a national semiconductor project backed by Japan's Ministry of Economy, Trade and Industry (METI), with goals of beginning 2nm mass production in the latter half of fiscal 2027 and going public around fiscal 2031. This collaboration is positioned as part of the design infrastructure buildout supporting that mass-production roadmap. The stance of advancing design environment preparation ahead of the start of mass production at the Chitose plant has also been reported as straight news by outlets such as The Nikkan Kogyo Shimbun and The Nikkei.
How Agentic AI Cuts TAT
Conventional EDA (Electronic Design Automation) tools have traditionally required human designers to set conditions at each stage, check results, and then proceed to the next step. According to the two companies' announcement, the integrated design environment combining Raads and InnoStack AI Super Agent has AI agents continuously oversee the flow from architecture exploration through implementation to sign-off. The TAT reduction is explained not as a result of increased computational power, but as an effect of process automation, orchestration, and data-driven optimization. It appears that the main source of this effect is the reduction of time humans would otherwise spend on verification and rework.
This mechanism traces back to the original version of Raads announced at SEMICON Japan on December 17, 2025. At that time, the stated goal—achieved by combining Raads with existing EDA tools—was "a 50% reduction in design time, a 30% reduction in cost, with availability beginning in fiscal 2026." Numerically, a 50% reduction in design time is equivalent to halving the time required, i.e., a 2x speedup in TAT. Whether today's "up to 2x TAT" target represents an independent new goal, or simply a restatement of the December 2025 figures with a different measurement basis or scope of processes, cannot be determined from the announcements and reporting available at this time. TECH+ (Mynavi), reporting on CEO Koike's keynote, covered the 30% cost-reduction target alongside a feature that automatically generates RTL (register-transfer level) circuit descriptions, and a feature that predicts power consumption, performance, and area (PPA) in a short time before final manufacturing—though it is reasonable to treat both as descriptions carrying over the goals set in December 2025.
Each instance of rework can require partially redoing the flow from architecture exploration through sign-off, potentially pushing back individual development schedules. This is why lead time is said to affect the speed of return on investment in leading-edge node design, and why TAT reduction is regarded as a key management metric: the view is that accumulated rework raises the risk of delaying the entire mass-production plan.
A Two-Front Partnership with Intel Foundry Reveals a Picture of Winners and Losers
Prior to this collaboration with Rapidus, Cadence had already announced, on June 8, 2026, a DTCO (design-technology co-optimization) partnership with Intel Foundry targeting the next-generation process "Intel 14A." Both Rapidus and Intel Foundry are chasing the leading-edge node mass-production race currently dominated by TSMC and Samsung. Rapidus is aiming to begin 2nm mass production in the latter half of fiscal 2027, while Intel Foundry is in the midst of launching its next-generation node, 14A, which follows its own 18A—said to be a 2nm-class node.
However, the Intel Foundry partnership is a multi-year DTCO (design-technology co-optimization) effort, currently at the stage of optimizing the PDK (Process Design Kit) for 14A going forward. This differs in character from the Rapidus collaboration, where the integration details and tool names have already been announced. Even so, within the span of a little over a month, Cadence has struck design collaborations centered on agentic AI technology with two leading-edge node challengers from entirely different lineages, at nearly the same time.
Rapidus is a fledgling foundry launched with support from Japan's Ministry of Economy, Trade and Industry, still at the stage of building up its mass-production track record. Intel Foundry, by contrast, is a veteran player that brought its own 18A process into mass production in 2025, but with 14A it too is in a position of building up a track record from scratch, while simultaneously aiming to win external customers for contract manufacturing and rebuild its brand. Though their backgrounds are contrasting, what they share—as challengers to next-generation nodes where TSMC and Samsung have taken the lead—looks to Cadence like a business opportunity.
Regardless of which of Rapidus or Intel Foundry reaches commercial mass-production velocity first, Cadence can maintain its position embedded within both companies' design flows. Viewed through the lens of profit distribution, the party guaranteed to benefit is Cadence itself. In the EDA industry, design tool revenue is often based on licensing agreements and is said not to be directly tied to a customer's mass-production volume.
The risk, on the other hand, falls on Rapidus and Intel Foundry, both of which are deepening their dependence on Cadence's design infrastructure even as they are still in the process of building a mass-production track record on these next-generation nodes. There is room for Rapidus's potential design customers to also join the side that benefits: if the AI-agent design environment proves genuinely usable, they stand to gain regardless of whether a mass-production contract materializes. The pattern of EDA vendors deeply integrating with a specific foundry's PDK (Process Design Kit—the complete set of design data matched to a manufacturing process) is itself an industry norm, but rolling this out across multiple foundries in the form of AI agents is a new development.
Design Tool Investment Piles Up While Mass-Production Contracts Remain at Zero
Zaikei Shimbun reports that Rapidus has yet to secure a single binding mass-production contract at this point. No matter how much the Cadence collaboration streamlines the design process, this figure is what defines Rapidus's business environment. The same outlet also reports the possibility that the design tool integration functions essentially as a customer lock-in strategy, and offers analysis suggesting Rapidus is roughly two years behind TSMC and Samsung in commercializing leading-edge nodes. A design-side target of up to 2x TAT does not necessarily translate into winning mass-production orders; the two are issues that should properly be treated separately.
Zaikei Shimbun further points out that there is not yet a single case of an LLM-driven autonomous EDA agent completing tape-out of an industrial chip without human intervention. In light of this point, it seems natural to conclude that the up-to-2x TAT target does not mean that final human judgment will be entirely removed from the design process. No matter how far automation on the design side advances, challenges on the mass-production side remain separate. Rapidus's planned monthly production capacity at the Chitose plant has been reported to rise from 6,000 wafers at startup to 25,000 wafers within the first year.
Specifics such as the names of customer companies that have actually adopted the tools, or the number of projects and samples underlying the calculation of the up-to-2x TAT target, are not disclosed in any announcement or report at this time (only the fact that the comparison baseline is "conventional flow" has been indicated). For Japanese fabless companies and design firms that will use the Chitose plant, how practically usable Raads proves to be in real-world work matters more than the TAT target figure itself. Whether this point is ever made public will serve as a measure of the distance between Rapidus's stated goals and actual demand.
This publication has previously reported that Rapidus has indicated a reference price of around ¥3 million to ¥3.5 million per 2nm wafer, a level roughly 30% cheaper than TSMC's estimated price of about $30,000. However, this figure is only a reference value, not an actual sales price. The state of mass-production contract acquisition is also a variable that will determine whether this price competitiveness can actually move customers.
The Main Battlefield Shifts from Mass-Production Speed to Control Over Design Infrastructure
Viewed in isolation, the Rapidus-Cadence collaboration can be summed up as a bilateral technology partnership built around an up-to-2x TAT target. But placed alongside the Intel Foundry partnership, its contours change substantially. Cadence has forged design collaborations centered on agentic AI technology with two challengers chasing leading-edge nodes, at nearly the same moment. A new yardstick is being added to the competitive axis in leading-edge semiconductors. Alongside speed to mass production, whose design toolchain development runs on has become a metric running in parallel.
As seen above, whether the names of adopting customers, the TAT measurement conditions, and the status of mass-production contracts will ever be filled in remains unclear. If anything, that very blank space is the litmus test for whether Cadence's strategy of securing design infrastructure first will actually pay off. The moment Rapidus lands its first mass-production contract, this collaboration will shift in status from a mere technical target to an investment backed by real demand. Controlling the design infrastructure and actually mass-producing chips for delivery to customers remain, for now, two separate paths running in parallel—and when those two paths converge will be the focus going forward.