Samsung Electronics has laid out a "CUBE" strategy for designing next-generation high-bandwidth memory (HBM) around four axes. At the Memory Executive Summit held during SEMICON Taiwan 2026 in Taipei on September 1, 2026, the company set targets for HBM5 of 2x the performance of HBM4E, a 20% improvement in performance per watt, and a 20% reduction in thermal resistance. However, when it comes to the follow-on zHBM, Samsung's own official materials and same-day media reports disagree on what the claimed "8x" figure is being compared against—HBM5 or HBM4E. To properly evaluate this new roadmap, it's necessary to separate three distinct levels of maturity before lining up multiplier claims: actual samples, development targets, and concepts.
CUBE consolidates HBM5 development goals into four axes
CUBE is a name formed from the initials of four design axes. "C" stands for capacity, "U" for utilization efficiency, "B" for bandwidth, and "E" for power/thermal efficiency. Capacity is increased by stacking vertically rather than expanding the substrate footprint; utilization efficiency is improved by tightening the arrangement of logic and memory to reduce latency; bandwidth is boosted by shortening the distance between dies; and efficiency is enhanced by reducing the power and heat required to move each bit. Rather than simply listing product names, Samsung has organized what it intends to improve from HBM4E to HBM5 to zHBM into these four design variables.
What's new this time are three concrete targets for the HBM5 currently under development. According to same-day reports from Newspim and News1, Samsung aims to double performance compared to HBM4E, improve performance per watt by 20%, and reduce thermal resistance by 20%. Thermal resistance here doesn't refer to heat tolerance temperature, but rather how difficult it is for generated heat to escape toward the heat-dissipation side. The lower this value, the easier it is to suppress temperature rise for the same amount of heat generated.
However, Samsung has not defined what it means by "performance" in this context. The meaning of "2x" changes depending on whether it refers to bandwidth per single stack, the total bandwidth across all stacks connected to an AI accelerator, or effective performance achieved in a specific AI workload. HBM5's absolute bandwidth and pin speed are not included in the information disclosed so far. Neither the number of stacks nor power consumption has been specified. The 2x figure is a design target, not a product specification or measured result.
Separating HBM4E's actual specs from HBM5's target values
HBM4E has real product data that can serve as a comparison baseline. On May 29, Samsung shipped 12-layer, 48GB customer samples, announcing stable operation at 14Gbps, a maximum of 16Gbps, and up to 3.6TB/s per stack. The company said this represents a 16% improvement in power efficiency and more than a 14% improvement in thermal resistance compared to HBM4. The start date for mass production is said to align with customer schedules and has not yet been finalized.
| Generation/Concept | Maturity as of September 2026 | Disclosed Performance | Process/Implementation | Undisclosed Conditions |
|---|---|---|---|---|
| HBM4E | 12-layer, 48GB samples shipped to customers | 14–16Gbps, up to 3.6TB/s, 16% power efficiency improvement, 14%+ thermal resistance improvement | 1c DRAM, 4nm base die | Mass production schedule, final customer-specific specs |
| HBM5 | Development targets and mockup | 2x performance vs. HBM4E, 20% improvement in performance per watt, 20% reduction in thermal resistance | 1c DRAM, 2nm base die, Heat Path Block | Absolute bandwidth, capacity, layer count, power consumption, test conditions |
| zHBM | Concept model; first-generation specs under development | Per Samsung's official materials: 4–8x vs. HBM5, 3x performance per watt, 50%+ reduction in thermal resistance | Hybrid copper bonding, multi-wafer bonding, stacking directly on xPU | Absolute bandwidth, configuration, yield, customers, product specs |
While HBM4E, as a customer sample, comes with concrete figures—48GB, up to 16Gbps, up to 3.6TB/s—both HBM5 and zHBM are described only in terms of performance multipliers, without absolute bandwidth figures or workload conditions. Comparing all three stages as though they were equivalent product spec sheets risks misjudging their actual level of disclosure maturity. At a March exhibition, Samsung also described HBM4E as reaching 16Gbps and 4.0TB/s, but in its May announcement of the 12-layer shipped samples, it stated a maximum of 3.6TB/s. If using the samples that have entered customer evaluation as the baseline, the latter figure is the safer one to use.
Competitors have also reached up to 16Gbps with HBM4E. SK hynix has shipped 12-layer HBM4E samples, announcing more than 20% improved power efficiency and a 17% reduction in thermal resistance compared to the previous generation. In other words, the 16Gbps pin speed is not a next-generation target unique to Samsung—it's already on the competitive frontier for HBM4E. To determine where HBM5's claimed 2x improvement actually comes from, one would need to separate the respective contributions of the 2nm base die and interface, the stacking structure, and thermal design.
The denominator behind the "8x" claim splits between HBM4E and HBM5
Samsung's Global Newsroom post dated August 5 stated that the next-generation interface system incorporating zHBM is expected to deliver roughly 8x the performance of HBM5. A technical explainer from August also used HBM5 as the comparison baseline, illustrating a range of 4x to 8x. It described performance per watt as being 3x and thermal resistance reduced by more than 50%.
Articles covering the September 1 presentation don't agree with each other. Newspim reported zHBM as 8x compared to HBM4E, while News1 and MoneyToday reported it as 8x compared to HBM5. Reports also diverged on thermal resistance, citing reductions ranging from 75% to 90%. Whether Samsung updated its design, used multiple zHBM configurations interchangeably, or the outlets simply used different comparison baselines or measurement points cannot be determined from publicly available information. The full presentation slide deck has also not been confirmed as publicly available.
Samsung's own published materials describe zHBM as 4–8x compared to HBM5, but same-day media coverage of the SEMICON Taiwan presentation split between 8x versus HBM4E and 8x versus HBM5. Since a target of 2x for HBM5 itself (compared to HBM4E) was also presented at the same time, it's impossible to link the zHBM multiplier across generations without first fixing the comparison baseline.
The difference in denominator is not trivial. If HBM5 is 2x HBM4E, and zHBM is 8x HBM5, and all these figures measure the same performance metric, then zHBM would work out to 16x HBM4E. On the other hand, if zHBM is reported as 8x HBM4E directly, the gap is half that. But because the definition of "performance" and the underlying configurations aren't aligned, this kind of multiplication cannot be used to predict actual real-world performance. What can be confirmed at this point is simply that the comparison baseline is not consistent across Samsung's own public materials.
Thermal resistance requires the same scrutiny. Between "more than 50%" and "75–90%," the remaining thermal resistance could differ by as much as fivefold. Results would also vary depending on whether the measurement point is the entire HBM stack or near the D2D PHY connecting the base die to the accelerator. Until Samsung discloses a baseline configuration, heat generation levels, and cooling conditions, the 75–90% figure cannot be definitively treated as an improvement over the August target.
The heat escape route is harder than the move to 2nm base dies
What is confirmed as a concrete technical difference for HBM5 is Samsung's plan to use 1c DRAM for the core die while moving the base die—which handles logic—from HBM4E's 4nm process to 2nm. Since the base die handles the connection and control functions with the accelerator, an advanced logic process allows for more circuitry and greater room for customer-specific customization. At the same time, as the number of layers and signal density increase, so does power density and heat generation. The move to 2nm alone does not solve the heat problem.
This is why Samsung is incorporating a Heat Path Block (HPB) into HBM5. This structure creates a dedicated thermal pathway from the heat source toward the top or sides, suppressing heat buildup inside the stack. Samsung has already completed implementation and verification of this using HBM4E, and presented plans at COMPUTEX 2026 to fully apply it starting with HBM5. However, the temperature and heat generation levels used during verification have not been disclosed, nor have the number of layers or cooling method.
With zHBM, the difficulty increases further. Whereas HBM was traditionally placed beside the AI accelerator, stacking it directly on top shortens wiring but also brings the heat source and memory closer together. Samsung has presented a concept using hybrid copper bonding and multi-wafer bonding to shorten signal paths and reduce thermal resistance. A design that allows customer-specific IP to be embedded in an intermediate layer would transform memory from a swappable component into part of the accelerator's own design.
Thermal countermeasures are a shared competitive battleground across the industry. SK hynix, with its iHBM for HBM5, aims to embed cooling components in areas where heat concentrates, targeting more than a 30% reduction in thermal resistance compared to previous products. Samsung's Heat Path Block creates a pathway to direct heat outward, while SK hynix's iHBM places cooling components near the heat source itself. The relative merits of the two approaches cannot be determined simply by comparing the size of their claimed reduction percentages. A fair comparison would require aligning measurement points and heat generation levels, as well as matching layer count and cooling method.
Three numbers to watch for 2029 and beyond
zHBM is not the name of a finished product—as of 2026, it represents a conceptual design direction. In an August 27 interview, Samsung's head of its U.S. operations indicated that first-generation specifications are still being developed and that commercialization is expected in 2029 or later, according to a Hankyung report. The sequence would involve first completing mass production and customer evaluation of HBM5, then bonding logic and memory together, and finally establishing the resulting cooling solution as a viable unified product.
Progress on the roadmap can be measured through three types of disclosure. The first is absolute bandwidth, broken down separately per stack and per AI accelerator. The second is performance per watt, with model and precision held constant and stack count and power consumption clearly specified. The third is a mass-production metric combining temperature data—showing measurement location and cooling conditions for thermal resistance—with post-stacking yield. Without these, figures like 2x and 8x may indicate a technical direction, but they don't provide numbers on which to base real-world AI system selection decisions.
As Samsung demonstrated with HBM4E, if it can ship samples to customers and disclose absolute speed, capacity, and thermal characteristics under the same configuration, then HBM5's claimed 2x improvement can become a verifiable product target. And if Samsung can further unify the comparison baseline for zHBM and disclose temperature and yield data for implementations incorporating hybrid copper bonding and Heat Path Blocks, then CUBE will move beyond being a roadmap slogan and become a design specification that reshapes how memory is positioned relative to AI accelerators.