On September 8, 2026, Samsung Electronics and ASML announced plans to introduce High-NA EUV into advanced DRAM mass production by 2028, with Samsung also joining industry efforts to develop 6×12-inch photomasks. On the same day, ASML and TSMC released a roadmap under which TSMC will begin using High-NA EUV in advanced-node mass production starting in 2030, aiming for a pilot line for the larger photomasks in 2031 and mass deployment of compatible exposure systems in 2033.
Lined up side by side, the sequence looks odd: both Samsung and TSMC are moving into High-NA EUV mass production before the larger photomasks are even finalized. But that time gap is precisely the substance of the transition strategy. Chipmakers first capture the higher resolution using today's 6-inch masks, then move to 12-inch masks once stitched exposures start to constrain throughput or large-area design.
Mass production in 2028 and 2030 arrives before 12-inch mask support
The four dates make clear that High-NA EUV and larger photomasks are not a single, unified equipment upgrade.
| Timeframe | Announced milestone | Status |
|---|---|---|
| By 2028 | Samsung adopts High-NA EUV for advanced DRAM mass production | Plan |
| From 2030 | TSMC adopts High-NA EUV for advanced-node mass production | Intent |
| 2031 | Pilot line for 12-inch masks established | Target |
| 2033 | 12-inch-compatible exposure systems deployed for advanced-node mass production | Target |
Samsung's adoption plan runs at least five years ahead of large-mask readiness. The direct benefits the company cited for DRAM are higher resolution to continue scaling and a simplified exposure process. Samsung did not disclose which DRAM generation or which layers would be targeted, nor how many fabs or tools would be involved. It also did not explain whether the 2028 DRAM process would require stitching—aligning two exposure fields at a boundary.
TSMC follows the same sequence. The company expects to use High-NA EUV in advanced nodes starting in 2030, with the number of applicable layers increasing in later generations. Meanwhile, the 12-inch pilot line is scheduled for the following year, 2031. ASML CEO Christophe Fouquet has explained that High-NA EUV will first spread using the current 6-inch masks, with 12-inch masks later boosting tool throughput. The goal of early adoption is minimum feature size and process-step reduction; the larger masks are meant to improve economics once production scale expands.
The optics that sharpen resolution cut the exposable area in half
High-NA EUV raises the numerical aperture of the projection optics to 0.55. ASML's TWINSCAN EXE:5000 offers 8nm resolution, and the company states it enables 1.7x finer patterns and 2.9x higher transistor density per single exposure compared to previous NXE tools. This describes the optical capability of the tool itself—not an actual density achieved in Samsung's or TSMC's products.
The trade-off is the area that can be exposed in a single pass. Because ASML continues to use the current 6-inch masks, it adopted anamorphic reduction optics that shrink the mask image by a factor of four along one axis and by a factor of eight along the other. This design preserves mask compatibility even at the higher numerical aperture, but it halves the exposure field on the wafer compared to conventional EUV.
Designs that fit within half the field can still be exposed in a single pass. Designs that exceed half the field must be split and exposed separately on each side, requiring high-precision boundary alignment. To support both cases, Intel Foundry provides customers with both a method for laying out circuits within the half-field and a PDK equipped with stitching functionality. Intel, which already uses High-NA EUV in mass production, demonstrates both that adoption is possible even with 6-inch masks and that doing so shifts more burden onto the design side.
Stitching increases the number of exposures and requires boundary alignment. Even as High-NA reduces the need for multi-patterning, splitting a large design into two fields means the tool's throughput isn't fully utilized. As a result, there is a natural time gap between the decision to adopt High-NA for resolution and the decision to move to 12-inch masks for throughput measured in good die per hour.
The 6×12-inch mask doubles area, and the retooling extends across the entire mask industry
The "12-inch mask" is not 12 inches square. The dimension being planned is 6×12 inches—doubling one direction of the current 6×6-inch mask. That doubles the area. If the longer side is aligned with the axis that High-NA optics shrink by a factor of eight, the full-field exposure area on the wafer—equal to that of conventional EUV—can be restored.
| Item | Current 6×6-inch | Proposed 6×12-inch |
|---|---|---|
| Exposure area under High-NA | Half the field of conventional EUV | Restores full field of conventional EUV |
| Timeline | Already available | Pilot line targeted for 2031, compatible tools for 2033 |
| Large designs | Stitching required | Aims for single full-field exposure |
| Main burden | Number of exposures, boundary alignment, design rules | Overhaul of mask fabrication, inspection, handling, and exposure tools |
Simply enlarging the dimensions wouldn't require waiting until 2031. An EUV photomask is not a transmissive original but a precision component that reflects extreme ultraviolet light via a multilayer coating. Research on mask blanks presented at SPIE Photomask Technology 2025 identified, for a 6×12-inch mask with an effective area of 104×264mm, the challenge of maintaining a uniform center wavelength for the reflective multilayer across a wider area. Scaling up the current ion-beam deposition process requires changes to both process conditions and equipment.
Once a blank is completed, a circuit pattern must be written onto it, defects inspected and repaired, and the mask cleaned and coated with a protective pellicle. The containers and handling equipment within the fab must also be adapted to the longer masks. In the exposure tool, the stage that holds and rapidly scans the mask must change as well. The reason Intel has spent more than three years calling not only on ASML but also on mask makers, automation companies, EDA vendors, and materials suppliers is that missing even one link in this chain would prevent the standard from reaching mass-production readiness.
TSMC and Samsung's participation changes the economics of standardization
The Large Size Mask Consortium conducts joint research as well as standards development and monitoring of global technology trends. Samsung's Korean-language announcement laid out its activities in this level of detail. The significance of TSMC and Samsung—which holds both DRAM and foundry businesses—joining the specification originally proposed by Intel lies less in the growing list of supporting companies and more in a shift in the investment calculus.
Companies that make mask blanks, write patterns, perform inspection, and handle logistics find it hard to recoup capital investment on a proprietary standard tied to a single chipmaker. If multiple major chipmakers adopt the same dimensions and interfaces, suppliers can sell compatible products to multiple customers. ASML, too, gains clearer visibility into demand for its 2033-generation tools. TSMC and Samsung's participation raises the likelihood that the industry can share costs broadly—ahead of, and separate from, the question of technical feasibility.
Standardization, however, does not make each company's High-NA process identical. Samsung is pursuing resolution and process simplification for 2028 DRAM. TSMC plans to expand the number of applicable layers in advanced logic from 2030 onward. Intel is already accumulating experience with mass production and stitching using current masks. Even once large masks become a shared standard, the process know-how each company has built around resist, mask correction, overlay, and yield for its specific products will not transfer.
Speaking to The Register, IDC's Andrew Buss compared this transition to the shift from 200mm to 300mm wafers. The comparison isn't about matching costs or timelines—it's meant to convey the scale of coordination required, since the transition can't succeed unless equipment makers, chipmakers, mask suppliers, and design teams align their standards within the same window of time.
In 2028, which DRAM generation and layers will Samsung apply High-NA EUV to, and how much real-world throughput and yield will it demonstrate? By 2030, it should become clear which layers TSMC processes with 6-inch masks and which designs require stitching. Furthermore, the 2031 pilot line will need to validate blank uniformity, defect inspection, and handling together, and by 2033 it must be revealed whether existing EXE tools can be retrofitted. Once those conditions are met, High-NA EUV will move from being simply a higher-resolution tool to becoming a mass-production platform where the competition is measured in how many large, advanced chips can be produced per hour.