On March 1, 1982, the Soviet probe Venera 13 landed on the surface of Venus. Its design lifespan was 32 minutes. In reality, it kept its camera and spectrometer running for 127 minutes before finally succumbing to 465°C heat and 92 atmospheres of pressure. More than 40 years later, no electronic circuit has yet managed to operate on the surface of Venus for more than a few hours.
The reason is simple. Silicon itself stops behaving like a semiconductor at high temperatures. Silicon's bandgap is 1.12 eV. As temperature rises, thermal energy kicks electrons from the valence band into the conduction band, causing current to leak into regions that should remain insulated. Once temperatures exceed roughly 250°C, transistors can no longer distinguish between on and off states, rendering integrated circuits nonfunctional.
Silicon carbide (SiC) has long been studied as a candidate for overcoming this barrier. The bandgap of 4H-SiC is about 3.26 eV—roughly three times that of silicon. Because the number of thermally excited electrons drops exponentially with a wider bandgap, SiC can in principle maintain semiconductor properties at far higher temperatures. Indeed, Philip Neudeck and colleagues at NASA's Glenn Research Center first reported 600°C operation of digital logic gates built from SiC JFETs (junction field-effect transistors) in 1998, and in 2017 achieved 521 hours of continuous operation in a simulated Venus environment at 460°C and 9.3 MPa.
However, these achievements shared a common limitation: they relied on custom processes using epitaxially grown films, making them difficult to transfer to mass-production lines.
Ion Implantation's Two Fatal Flaws
Ion implantation is the standard technique for introducing impurities into a crystal during semiconductor mass production. Accelerated ions are driven into the crystal surface to dope specific regions. It is a mature technology used in silicon integrated circuit manufacturing for decades, and existing fabrication equipment can be used as-is.
Ion implantation has also been attempted with SiC, but fabricating JFETs this way has faced two serious problems.
First, uncontrollable threshold voltage. When ions are implanted into a crystal, a phenomenon called "channeling" occurs, in which ions penetrate deeper along the crystal axis than intended. Impurities that should stay at a designed depth instead reach further than expected. In conventional top-gate structures—where the gate sits above the channel—this excess penetration alters the impurity concentration in the channel, causing the threshold voltage to deviate from its design value by more than 2V. Threshold voltage is the most fundamental parameter determining a transistor's operating point. A deviation of 2V makes it impossible to design integrated circuits combining multiple transistors.
Second, substrate leakage at high temperatures. Conventional devices have been fabricated on semi-insulating SiC substrates. While these substrates exhibit high insulation resistance at room temperature, rising temperatures generate more thermally induced carriers within the substrate itself, increasing leakage current between devices. Near 600°C, this leakage becomes comparable in magnitude to the signal current, causing the circuit to lose its function.
These two issues have continued to block the practical implementation of ion-implanted SiC integrated circuits for high-temperature applications.
A Reversed Idea: Placing the Gate "Below"
A research group led by Associate Professor Kaneko, along with master's student Shuya Shibata (at the time of the research) and Professor Tsunenobu Kimoto, devised a structure that solves both problems simultaneously. The results were published as an invited paper in APL Electronic Devices on August 17, 2026 (DOI: 10.1063/5.0346734).
The key innovation is placing the gate electrode "below" the channel.
In conventional top-gate structures, when the channel region is formed via ion implantation, channeling causes impurities to penetrate deeper than the channel itself, shifting the channel's effective impurity concentration away from the design value. In the bottom-gate structure, the gate layer is pre-formed below the channel. Even when ions channel deeper than designed, the gate layer is waiting there to receive them. The penetrating impurities are absorbed as part of the gate layer, leaving the channel's concentration profile unaffected.
Associate Professor Kaneko explained: "By placing the gate beneath the channel, we can absorb the distortion caused by ion channeling during implantation."
With this design, the gap between the designed and measured threshold voltage at 400°C came in under 0.1V—more than a 20-fold improvement over the 2V-plus deviation seen in conventional structures.
An Isolation Structure That Doesn't "Trust" the Substrate
Another key innovation is device isolation using a double-well structure.
Conventional devices relied on the insulating properties of the semi-insulating SiC substrate to electrically isolate devices from one another. While semi-insulating substrates have sufficiently high resistivity at room temperature, rising temperatures increase the intrinsic carrier concentration, degrading insulation performance. This is an inherent property of the material and cannot be avoided through device structure alone.
The research group took a different approach. Rather than "trusting" the substrate as an insulator, they adopted a structure that actively encloses each device using pn junctions. Each transistor is surrounded by a double-layer structure of p-type and n-type wells (a "double well"), forming a reverse-biased pn junction with the substrate. This junction maintains a depletion layer even at high temperatures, blocking leakage current through the substrate.
As a result, leakage current at 600°C was reduced by an order of magnitude compared to the value shown by conventional structures at 400°C (absolute values for both comparison points were not disclosed in the publicly available materials confirmed for this article). The activation energy of the remaining leakage was confirmed to match approximately half the bandgap of 4H-SiC (about 1.6 eV). This indicates that the leakage has reached the intrinsic thermal generation limit of SiC—that is, the theoretical lower bound set by the material itself. In principle, there is almost no room left to further reduce leakage through structural improvements alone.
| Item | Conventional Structure (Top-Gate + Semi-Insulating Substrate) | This Study (Bottom-Gate + Double Well) |
|---|---|---|
| Threshold voltage design deviation (400°C) | Over 2V | Under 0.1V |
| Leakage current (operating temperature) | Already problematic at 400°C | At 600°C, 1/10 or less of the 400°C value from conventional structures (absolute values undisclosed) |
| Leakage-limiting factor | Degradation of substrate's semi-insulating property | Intrinsic thermal generation in SiC (theoretical limit) |
| Manufacturing process | Epitaxial growth (custom) | Ion implantation (compatible with standard mass production) |
| Demonstrated operating temperature | 500°C (NASA, circuit level) | 600°C (device level) |
NASA's 5,000-Hour Track Record and the Separate Axis of "Mass-Production Compatibility"
The most advanced work in high-temperature SiC integrated circuits comes from NASA's Glenn Research Center. Neudeck's team ran a SiC JFET integrated circuit incorporating more than 175 transistors continuously for over 5,000 hours in 500°C air, and separately achieved 521 hours of operation in a simulated Venus environment at 460°C and 9.3 MPa. However, these devices were fabricated using a proprietary process (JFET-resistor technology) that forms epitaxially grown films and resistors within the same SiC layer—not one designed for deployment on mass-production equipment.
Kyoto University's achievement surpasses NASA's demonstrated temperature (500°C) in absolute operating temperature (600°C), but for now remains limited to single-device characterization; long-term circuit-level operation has not yet been demonstrated. Rather than competing directly, the two efforts are tackling different axes of the challenge. NASA is addressing "long-term circuit reliability" head-on, while Kyoto University is tackling "compatibility with mass-production processes."
Three Challenges That Remain Beyond 600°C
This transistor currently operates in normally-on mode (current flows at zero gate voltage). Building low-power logic circuits requires normally-off devices, where current stops at zero gate voltage. Professor Kimoto's group has already demonstrated complementary SiC JFET logic gates operating at 350°C, and achieving normally-off operation with the new structure is the next goal.
Second is long-term reliability. Whether continuous operation at 600°C can be sustained for thousands of hours remains unverified. While NASA's devices showed less than 10% characteristic change even after exceeding 5,000 hours at 500°C, material degradation and wiring oxidation progress faster at 600°C.
Third is packaging and implementation. Even if the device itself withstands 600°C, this achievement is meaningless unless the surrounding encapsulation materials, wiring materials, and substrate can endure the same temperature.
The vision of conducting meteorological and seismic observations on the surface of Venus over multiple days remains, for now, at the stage of "theoretical material possibility." Still, the fact that threshold voltage can be controlled to within 0.1V precision using a standard ion-implantation process represents a result showing that high-temperature SiC integrated circuits can potentially transition from custom laboratory devices to mass-production technology based on standard design rules. The significance of the number 600°C lies less in the temperature itself than in the fact that the path to reaching it runs through existing manufacturing infrastructure.