The biggest physical barrier facing modern computer engineering is the delay and power consumption associated with the massive data transfers between processors and memory. This so-called von Neumann bottleneck has become even more severe with the proliferation of neural networks whose parameter counts now reach into the hundreds of millions or even hundreds of billions. Particularly for small, power-constrained sensors and edge devices, demand continues to grow for completing real-time processing locally rather than relying on cloud data centers.
One approach to solving this energy problem is research into analog crossbar memory arrays that perform multiply-accumulate operations directly inside or adjacent to the memory cells. However, each of the non-volatile memory technologies currently under consideration carries its own set of physical trade-offs and limitations.
A research team led by Associate Professor Jean Anne Incorvia of the Microelectronics Research Center in the Department of Electrical and Computer Engineering at the University of Texas at Austin, together with Samuel Liu, a recent PhD graduate from her lab, conducted joint research with the Corporate Research division of TSMC, the world's largest semiconductor foundry. The team fabricated an array of spin-orbit torque magnetic random access memory (SOT-MRAM) on a standard 300-millimeter wafer used in mass semiconductor production, and carried out detailed physical characterization of the devices. The results were published as a peer-reviewed paper in the journal Science Advances.
How a Three-Terminal Separated Structure Enables Fast Writing and Longer Lifespan
Among non-volatile memory types, magnetic memory retains information via the direction of magnetization even after power is switched off. Spin-transfer torque magnetic memory (STT-MRAM), which has been the subject of ongoing commercialization efforts, is a two-terminal device based on a magnetic tunnel junction (MTJ), in which an extremely thin tunnel insulating layer (magnesium oxide) is sandwiched between two ferromagnetic layers.
To rewrite information in STT-MRAM, current is passed directly and vertically through the tunnel insulating layer, transferring the angular momentum of spin-polarized electrons to the magnetization of the free layer. In this structure, the insulating layer is subjected to continuous high electrical stress during writing, which shortens the device's write endurance. Additionally, achieving fast magnetization switching requires a large write current, which sharply increases the risk of dielectric breakdown—constraining write speeds to typically several tens of nanoseconds. Because the read and write paths are the same, the risk of read disturb—where a read operation inadvertently triggers a write—could not be fully eliminated either.
In contrast, the SOT-MRAM used in this study adopts a three-terminal structure in which a heavy metal layer, such as platinum or tungsten, is placed directly beneath the MTJ. During writing, current flows horizontally through the underlying heavy metal layer rather than through the MTJ itself. As electrons flow through the heavy metal layer, the spin-orbit interaction (via the spin Hall effect and Rashba effect) causes electrons with upward and downward spins to polarize and accumulate at opposite interfaces. This spin current exerts a pure spin torque on the ferromagnetic free layer directly above it, rapidly reversing its magnetization.
Because of this three-terminal mechanism, the write current never passes through the tunnel insulating layer. This allows a large current to flow for a short time without damaging the insulating layer, enabling high-speed operation while suppressing the degradation of write endurance. Since the read current still passes through the MTJ via a separate path, as in conventional designs, the read and write paths are physically completely separated.
On the other hand, this structure results in a larger cell area compared to STT-MRAM, creating a trade-off that disadvantages integration density. Furthermore, as an inherent characteristic of magnetic memory, the direction of magnetization can only stably hold two states—upward or downward (corresponding to high-resistance and low-resistance states). Unlike resistive RAM (RRAM) or phase-change memory (PCRAM), which can record continuous or multi-level resistance values (multi-value states) in a single cell, applying this technology directly to analog multiply-accumulate circuits has structurally been difficult.
The research team accepted this physical constraint and instead designed an approach that turns the binary nature of two-state memory into an advantage. By combining quantization-aware training (QAT), which restricts weight parameters to three values—"−1, 0, +1" (equivalent to 2 bits)—with probabilistic switching behavior, the team built a framework for applying binary magnetic memory to neural network computation.
Device Physics Measured on a 300-Millimeter Wafer, Compared with Other Technologies
The engineering value of this research lies not merely in small-scale laboratory prototyping, but in the fact that the team integrated a 4-kilobit memory array on a standard 300-millimeter silicon wafer using TSMC's manufacturing facilities, obtaining measurement data at wafer scale.
The research team extracted 100 devices from the fabricated array for detailed characterization. The results showed an average tunneling magnetoresistance ratio (TMR ratio) of 166% (against a nominal target of 150% or higher), and confirmed reliable magnetization switching with an extremely short pulse width of 2 nanoseconds at an operating voltage below 1 volt. Write noise was extremely low at 0.1%, and endurance testing showed no degradation in device characteristics even after applying more than 10^12 (one trillion) write pulses.
Regarding energy consumption, the paper itself reports an average measured energy consumption of 350 femtojoules (350 × 10^-15 joules) per write operation. Meanwhile, some technology reports covering this result have also cited a figure of "2 picojoules per write." This 2-picojoule figure likely reflects an estimate of the energy consumption of the entire evaluation system, including peripheral wiring, as opposed to the 350-femtojoule figure, which represents the switching energy of the individual device itself. As the fundamental data describing the microscopic switching characteristics of the device itself, the 350-femtojoule figure explicitly stated in the paper serves as the baseline.
| Memory technology | Write speed | Write energy | Endurance (cycles) | Number of stable states | Device-to-device variation | Key physical constraints |
|---|---|---|---|---|---|---|
| SOT-MRAM (measured in this study) | 2 ns | 350 fJ | > 10^12 | 2 (binary) | ~10% | Larger cell area; limited to 2 states |
| STT-MRAM | ~90 ns | 27 pJ | 10^6–10^12 | 2 (binary) | Moderate | Insulator degradation, slow speed |
| RRAM (resistive) | 10 ns–5 ms | 100–787.5 pJ | 10^6–10^10 | Multi-level (analog) | High (filament-driven) | Write variability, filament control |
| PCRAM (phase-change) | ~50 ns | 1 pJ–2 nJ | 10^7–10^9 | Multi-level (analog) | Moderate to high | High reset power, thermal crosstalk |
| ECRAM (electrochemical) | ~100 ns | 3.5 µJ | 10^7–10^9 | Multi-level (analog) | Low to moderate | Difficulty integrating liquid/ion transport |
Compared with other competing non-volatile memory technologies, SOT-MRAM's 2-nanosecond write speed is significantly faster than STT-MRAM's roughly 90 nanoseconds and PCRAM's roughly 50 nanoseconds. Its write energy of 350 femtojoules is also several orders of magnitude lower than the hundreds of picojoules required by RRAM or the nanojoule-scale energy required by PCRAM.
However, as the table shows, while RRAM and PCRAM can create intermediate resistance values within a single cell to perform analog multi-level multiply-accumulate operations, SOT-MRAM is strictly limited to two states. In addition, measurements of variation across the fabricated device population found that the ratio of standard deviation to mean was 9.4% for the high-resistance state and 10.2% for the low-resistance state—confirming roughly 10% variation. How this physical variation affects computational accuracy became the next subject of investigation.
Neural Network Simulations Based on Measured Data
All of the AI processing evaluations conducted in this study are numerical simulations run in software, incorporating measured device parameters. What was actually fabricated and measured on TSMC's wafer were individual SOT-MRAM devices and memory arrays—not a fully functioning AI accelerator chip that runs a neural network end-to-end in hardware.
Using "CrossSim," a crossbar array simulator developed by Sandia National Laboratories, and the machine learning framework PyTorch, the research team built a model incorporating the measured TMR ratio, the write probability distribution at 2 nanoseconds, resistance variation, and noise data, and used it to evaluate three tasks.
1. LeNet-5 Inference Simulation with 2-Bit Quantization
The team ran an inference simulation on "LeNet-5," a convolutional neural network used for image recognition on the MNIST handwritten digit dataset. Two SOT-MRAM cells were combined to represent a single weight value (+1, 0, −1), and quantization-aware training (QAT) was applied.
Against a theoretical verification accuracy of 98.2% at full precision (32-bit floating point), the ideal SOT-MRAM characteristic model maintained equivalent accuracy. Furthermore, a simulation incorporating only the write noise within a single device (0.1%) achieved an average recognition accuracy of 95.1% (standard deviation 0.2%).
However, when the roughly 10% device-to-device variation measured on the wafer was introduced into the model and 20 trials were run, recognition accuracy dropped to an average of 88% (standard deviation 3.2%)—a decline of about 7 percentage points. The simulation demonstrated concretely how variation in individual device resistance directly translates into computational error when currents are summed on an analog crossbar.
2. Binary Neural Network Training Using Probabilistic Switching
Next, the research team ran a training simulation for a multilayer perceptron (784-200-200-10 architecture) using the Fashion-MNIST clothing image dataset (60,000 training samples, 10,000 validation samples).
When the pulse voltage applied to SOT-MRAM is set near the switching threshold, a physical phenomenon occurs in which magnetization reverses probabilistically. The team incorporated this probabilistic switching characteristic as a lookup table and used it in the stochastic gradient updates of the Adam optimization algorithm.
In simulations using a lookup table derived from a single device under a 10-nanosecond pulse, training convergence equivalent to that of an ideal binary neural network was confirmed. However, measurements at a 2-nanosecond pulse showed that the voltage window in which probabilistic switching occurs widens to approximately 0.5 volts, compared with approximately 0.05 volts at 10 nanoseconds—indicating that control becomes more difficult at the faster pulse width.
3. Analysis of Probabilistic Graphical Modeling
As a third evaluation, the team examined applying the technology to sampling processes in probabilistic graphical models. Here, they analyzed the interaction between the magnitude of the TMR ratio, the distribution of the switching probability curve, and conductance noise, and theoretically demonstrated that securing a high TMR ratio helps reduce sampling error in hardware implementations.
While these three sets of results represent highly accurate predictions grounded in measured physical properties, it should be noted that they do not represent the operational results of a fully integrated hardware chip that includes control circuitry and analog-to-digital converters (ADCs).
Remaining Challenges for Commercial Edge Deployment and Integration Hurdles
Professor Incorvia has expressed the view that accelerators based on SOT-MRAM could eventually replace CPU-based AI accelerators in edge devices such as sensors. However, realizing this vision at an industrial scale still requires clearing a number of engineering hurdles.
Among the challenges the authors themselves identify in the paper are suppressing device-to-device variation and further improving the TMR ratio. As the simulations above demonstrated, resistance variation among devices alone caused recognition accuracy to drop sharply from 95.1% to 88%. In crossbar circuits that perform signal summation in the analog domain, non-uniformity among devices directly affects inference quality. Achieving atomic-layer-level thickness uniformity in the ferromagnetic and heavy metal layers during the manufacturing process will be necessary.
Another challenge is the area penalty inherent to SOT-MRAM's three-terminal structure. Because each cell requires a contact for the heavy metal wiring that carries the write current, achieving high integration density is more difficult than with simpler two-terminal devices such as STT-MRAM or RRAM. Achieving higher density will require innovations in cell layout and the application of three-dimensional stacking technology.
Data on manufacturing yield, production cost, and heat generation or crosstalk when integrated on the same die as CMOS logic circuits are also not included in this device-level evaluation. Whether a binarized architecture can maintain practical accuracy beyond small benchmarks such as MNIST and Fashion-MNIST, when applied to large-scale real-world image recognition or natural language processing models, also remains a subject for future verification.
The research team plans to continue improving the magnetic properties of the devices and to work on reducing variation across the entire wafer. While confirming a 2-nanosecond, 350-femtojoule device on a 300-millimeter wafer marks a step forward, whether this translates into processors embedded in everyday edge devices will depend on future progress in process scaling and circuit integration technology.