JEDEC has published a new DRAM standard, JESD330-4, that brings HBM4 closer to standard packaging. Its name is Standard Package High Bandwidth Memory 4, abbreviated SPHBM4. While using the same DRAM stack internals as HBM4, it narrows the host-side connection down to 512 data signals. AI accelerators want to maintain memory bandwidth, but the silicon interposer's area and wiring density are becoming a heavy burden. SPHBM4 is a standard that reduces this pressure from the packaging side rather than from the memory cells.
The significance of this announcement isn't that "HBM suddenly becomes cheap commodity memory." According to JEDEC's explanation, SPHBM4 uses the same memory core layer as HBM4 DRAM, so the inherent difficulty of stacked DRAM itself remains. What changes is the pathway connecting the compute die and the memory. The wide 2048-signal HBM4 connection is converted to 512 signals via 4-to-1 serialization, aligning it with bump pitch and wiring conditions that can be handled even with organic substrates. This is where the design of AI chip implementation cost and the amount of memory that can be mounted on a single package comes into play.
Standardizing the Narrowing to 512 Signals
The key point of JESD330-4 is that, without discarding the HBM4 DRAM stack, it changes the form of the signals sent externally via a different buffer die. JEDEC's standard page explains that SPHBM4 uses the same DRAM stack as HBM4 DRAM (JESD270-4) but adopts a different buffer die to make it easier to assemble with standard packaging. In other words, what's being standardized is not new memory cells, but the interface that sits between the HBM4 stack and the compute die.
At the preview stage in December 2025, JEDEC explained that while HBM4's interface has 2048 data signals, SPHBM4 aims for the same bandwidth using 512 data signals with 4-to-1 serialization. This direction is maintained in the now-published JESD330-4. Each SPHBM4 channel has a 16-bit DDR data bus, running four times faster than the corresponding HBM4 channel's 64-bit data bus.
This conversion reduces the number of wires but increases signal speed and the workload on the buffer die. HBM4 uses a wide path at relatively lower speed. SPHBM4 narrows the path width and tries to carry the same amount of data using faster signals. JEDEC states that SPHBM4, like HBM4, has a distributed interface where channels are independent of one another and not necessarily synchronized. While inheriting this independent channel structure, SPHBM4's design lowers the density of external connections.
What Gets Cheaper Isn't the Memory Itself
SPHBM4's "lower cost" doesn't mean the unit price of the DRAM stack drops dramatically. According to JEDEC's explanation, SPHBM4 uses the same memory core layer as HBM4. Tom's Hardware also points out that the advanced assembly involving stacked DRAM, TSVs, known-good-die screening, and the buffer die all remain. Therefore, this isn't a technology that drops down to the same price range as mass-produced graphics memory like GDDR7.
What could decrease is primarily the packaging implementation cost for AI accelerators. HBM4 uses extremely wide parallel connections to achieve high bandwidth. While this approach is strong on power efficiency, it demands large wiring resources around the compute die, tightening constraints on silicon interposers and high-density packaging. By narrowing to 512 data signals, SPHBM4 makes it easier to use what JEDEC calls a "relaxed bump pitch," bringing implementation closer to organic substrates.
Here it's easy to misread the difference from GDDR7. JEDEC's GDDR7 standard is an extension of general-purpose external memory that defines the functions, packaging, and pin assignments of graphics-oriented SGRAM. SPHBM4, though also a JEDEC standard, is stacked memory intended to deliver HBM4-class bandwidth right next to the compute die. Tom's Hardware cites the remaining HBM stack and advanced packaging processes as reasons SPHBM4 is unlikely to become a replacement for GDDR7. It's more accurate to view it not as a candidate for cheaply replacing memory chips in consumer GPUs, but as a candidate for reducing interposer area and wiring difficulty in the massive packages used in AI servers.
A Path to Increasing Capacity
Explaining why SPHBM4 matters for AI accelerators in terms of cost alone gives too narrow a picture. In its December 2025 preview, JEDEC explained that because SPHBM4 uses the same memory core layer as HBM4, the capacity capability per stack is identical. Beyond that, it noted that organic substrate wiring can more easily accommodate longer channel lengths from the SoC to memory, potentially allowing an increase in the total number of SPHBM stacks.
In AI accelerators, even if you increase the number of compute units, you can't fully utilize performance if there isn't enough nearby memory capacity and bandwidth. While HBM4 extends bandwidth, its wide 2048-signal connection puts pressure on the package's periphery, bumps, and wiring layers. Since SPHBM4 reduces the number of host-side signals while maintaining the same stack capacity, it expands the option of placing more memory closer to the compute die.
This matters especially for designers who struggle to secure large quantities of cutting-edge silicon interposers. In large-scale AI chips, it's often not the compute die itself but the supply of surrounding HBM, substrates, and advanced packaging that constrains product planning. What SPHBM4 aims for isn't to completely eliminate this bottleneck, but to widen the range of implementation options available to designers. Products prioritizing performance above all will still stick with conventional HBM4 or HBM4E, while products prioritizing capacity and implementation flexibility will have SPHBM4 as a candidate.
Remaining Challenges: Buffer Die and Power
The design that narrows things down to 512 signals shifts the wiring problem elsewhere. In SPHBM4, the buffer die and PHY that convert HBM4's wide channels into a narrower external interface bear a heavy role. Tom's Hardware points out on this matter that while fewer signal lines could mean fewer drivers and receivers, the high-speed serial PHY consumes power, so it cannot be definitively called low-power without implementation details.
The same applies on the manufacturing side. Even if the silicon interposer can be avoided, SPHBM4 still requires stacked HBM DRAM and a dedicated buffer die. The division of labor among DRAM manufacturers, foundries, the OSATs handling assembly, and AI chip designers is not simple either. With JEDEC's publication of the standard, a common foundation now exists for controller and package design. However, the pricing, yield, power consumption, and implementation density of mass-produced products cannot be judged until actual products from each company appear.
The numbers to watch next are the stack count, memory capacity, package substrate, and measured power consumption of products adopting SPHBM4. JESD330-4 has created a standard for handling HBM4-class bandwidth with 512 signals. What the market will confirm is how far that standard actually eases the memory constraints faced by AI accelerators.