On October 21, 2026, Tohoku University announced the launch of T-CHIPS, a research and development consortium that promotes advanced semiconductor packaging and heterogeneous integration. The initiative focuses on technologies that stack multiple semiconductor chips or combine chips with different functions, and the university will pursue the research jointly with companies such as materials and equipment manufacturers. It is setting up a consultation desk so that companies can use the university's research facilities. The aims are to bring research results to industry and to reflect the technical challenges companies face in the research itself. How the new organization will change corporate R&D becomes clearer when you look at the role of each facility and its terms of use.
T-CHIPS Supports Corporate Use of Research Facilities
At the core of T-CHIPS are Tohoku University researchers working on the project "3D Heterogeneous Integration Technology for Realizing Edge AI Semiconductors," part of the Japan Science and Technology Agency (JST) "Next-Generation Edge AI Semiconductor Research and Development Program." The principal investigator is Professor Tetsu Tanaka of the university's Graduate School of Biomedical Engineering. Besides Tohoku University, seven private companies and three other universities take part in the joint research and development. However, this reflects the size of the existing research project, not the membership of the newly launched T-CHIPS.
Tohoku University set up the consortium not only to transfer its research results to companies, but also to reflect the technologies companies will need in the future in the direction of its research. It aims to go beyond its existing joint research partners, increasing points of contact with new companies and broadening both where its results can be used and what research challenges it takes on. In addition to semiconductor materials and equipment manufacturers, it expects to work with companies engaged in design and manufacturing.
T-CHIPS will perform two main functions. One is a "concierge function" that introduces companies to research sites and researchers suited to their development challenges. The other is technical exchange and human resource development through study groups and briefing sessions. According to Tohoku University's detailed announcement, research facilities that companies have mainly used through joint research will also become available via the consortium. The facilities are expected to be used, for example, to produce test wafers needed to develop equipment and components, and to demonstrate semiconductor manufacturing processes that use new materials. The university intends to widen opportunities to use its facilities not only for companies that evaluate finished semiconductor devices, but also for those that develop the materials and equipment supporting manufacturing processes.
Testing Chip Stacking and Heterogeneous Integration Through Prototypes
Advanced packaging is a technology that builds sophisticated semiconductor devices by mounting manufactured chips on wiring substrates and stacking or integrating multiple chips. Compared with front-end processes, which form transistors and wiring on silicon wafers, it belongs to the back-end stage, which deals with how manufactured chips are connected and made to function as a single device. As semiconductors become more powerful, techniques for efficiently combining multiple chips, rather than relying on a single chip, are growing in importance.
Heterogeneous integration, meanwhile, refers to technology that combines different types of semiconductor chips or materials. One example is a configuration that pairs a processor for computation and memory with a silicon photonics chip for optical communication. The scope also includes MEMS (micro-electromechanical systems), which have minute mechanical structures, and technologies for integrating different materials, such as silicon and compound semiconductors. Because components with different functions and manufacturing processes are combined, developers must consider not just connecting chips but also processing precision, bonding methods, and characteristics after assembly.
Developing such technologies requires prototyping and verification using actual materials and devices. A company developing a new material must confirm whether it can be handled in existing semiconductor manufacturing processes and whether the necessary processing and bonding are possible. For companies developing manufacturing equipment, too, an environment where test wafers can be prepared to verify equipment performance and processing precision is important. The test wafer production support and process demonstrations with new materials that T-CHIPS advertises are meant to address these development challenges.
The hope is that, beyond simply introducing existing research results to companies, the consortium will let problems companies want to solve be verified on the university's facilities and, where appropriate, develop into joint research. That said, this announcement lays out the organization and support policy for such activities; it does not announce a demonstration of the performance or mass-producibility of a new semiconductor chip. Going forward, what prototyping and analysis companies' specific development challenges lead to will be a basis for judging the initiative's results.
SIRC, GINTI, and NanoTerasu: Different Facilities and Terms of Use
The research sites T-CHIPS supports for corporate use include Tohoku University's Smart-System Integration Research and Development Center (SIRC) and the Three-Dimensional Super Chip Manufacturing Base (GINTI) in Natori, Miyagi Prefecture. The Micro System Integration Center (μSIC) is also covered, and for the NanoTerasu synchrotron radiation facility, T-CHIPS will support joint research that uses Tohoku University's allocation. Because the facilities differ in the wafer sizes they handle, their research equipment, and their analysis methods, companies must choose the appropriate site for their development work.
Based on the facility guide on the T-CHIPS official website, the roles and usage methods of the three main facilities are summarized below.
| Research site | Main equipment and scope | Usage method stated in the official guide |
|---|---|---|
| SIRC (Tohoku University, Aoba-yama) | Covers everything from design to microfabrication, bonding, and packaging. Handles items from small chip pieces to 4-inch wafers | In principle, via a Tohoku University laboratory. Access through the consortium is planned for the future |
| GINTI (Natori, Miyagi Prefecture) | R&D prototyping line supporting 200 mm and 300 mm wafers. Enables device prototyping and process demonstrations with new materials | Contact point is the Fukushima Laboratory or the Tetsu Tanaka Laboratory. Access through the consortium is planned for the future |
| NanoTerasu (Tohoku University, Aoba-yama New Campus) | Material analysis and manufacturing process evaluation using synchrotron radiation | Trial opportunities will be provided through joint research with Tohoku University laboratories, using the university's coalition allocation |
This comparison organizes each facility's scope and usage method based on the official guide as of October 2026. It does not indicate which facility is superior in equipment performance or cost-effectiveness. SIRC covers processing, bonding, and packaging from small chip pieces to 4-inch wafers; GINTI handles prototyping with 200 mm and 300 mm wafers; and NanoTerasu provides analysis and evaluation using synchrotron radiation. Each plays a different role.
For example, a company considering prototyping a device on 300 mm wafers can confirm from the official guide that GINTI supports them. Because that differs from the 4-inch wafers SIRC handles, the same equipment cannot necessarily substitute. Use of NanoTerasu is through joint research with Tohoku University, so becoming a T-CHIPS member does not mean a company can freely use the facility or its instruments. Companies should check not only the purpose each facility serves but also what procedures and research arrangements are required.
What Tohoku University has presented is a policy of making these research sites easier to use through the consortium. However, the official website also lists the conventional laboratory-based points of contact, so access to facilities through the consortium has not yet fully started. Companies considering use will need to organize the target materials, wafer sizes, and required processing and analysis, and then consult on the appropriate facility and procedures.
Fiscal 2026 Membership Fee Is Free; Facility Fees Need Separate Confirmation
The annual membership fee for corporate members of T-CHIPS is 200,000 yen per unit. The fee applies from April 1 to March 31 of the following year, but fiscal 2026, the inaugural year, is free. Academic members, who are faculty and researchers affiliated with universities and independent administrative institutions, also pay no fee.
To join, corporate applicants must submit an application form to the secretariat and undergo review by the steering committee. Academic members require a recommendation from an officer. However, the fee waiver for fiscal 2026 does not mean that research facility usage fees are also waived. Membership conditions and the terms of use for individual facilities are separate, so facility fees, reservation methods, and the procedures required for joint research must each be confirmed.
For exchange among members, the official website states plans to hold study groups and lectures four times a year. The consortium will also work on human resource development in cooperation with the Semiconductor Creativity Hub (S-Hub), and plans to collaborate with organizations in the Sendai area such as Tohoku Microtec and MEMS Core. By providing opportunities for researchers and companies to share technical challenges and development needs, in addition to support for facility use, it aims to lead to new joint research and technology development.
A kickoff meeting is scheduled for December 4, 2026, at Muromachi Mitsui Hall & Conference in Tokyo. Advance registration is required; attending the meeting is free, while the networking reception charges a fee. For companies considering participation, it will be a chance to learn about the consortium's activity policy and how to use the research facilities. Of particular interest will be how far the meeting clarifies practical matters that the announcement alone does not reveal, such as equipment usage fees, reservation methods, and the terms of joint research.
The key to judging T-CHIPS's results is which facilities the development consultations from companies actually lead to prototyping and analysis on. Advanced packaging and heterogeneous integration involve a wide range of technologies, including materials, equipment, design, and manufacturing, so it is not easy for individual companies to assemble all the necessary facilities and expertise themselves. If T-CHIPS makes it easier to reach suitable research facilities and researchers for their development challenges, companies will have more options for verifying new materials and manufacturing technologies. Going forward, the focus will be on how concretely the terms of use for each facility are defined and whether they lead to actual prototyping and joint research.